skip to main content
research-article

ShieldNVM: An Efficient and Fast Recoverable System for Secure Non-Volatile Memory

Published:18 May 2020Publication History
Skip Abstract Section

Abstract

Data encryption and authentication are essential for secure non-volatile memory (NVM). However, the introduced security metadata needs to be atomically written back to NVM along with data, so as to provide crash consistency, which unfortunately incurs high overhead. To support fine-grained data protection and fast recovery for a secure NVM system without compromising the performance, we propose ShieldNVM. It first proposes an epoch-based mechanism to aggressively cache the security metadata in the metadata cache while retaining the consistency of them in NVM. Deferred spreading is also introduced to reduce the calculating overhead for data authentication. Leveraging the ability of data hash message authentication codes, we can always recover the consistent but old security metadata to its newest version. By recording a limited number of dirty addresses of the security metadata, ShieldNVM achieves fast recovering the secure NVM system after crashes. Compared to Osiris, a state-of-the-art secure NVM, ShieldNVM reduces system runtime by 39.1% and hash message authentication code computation overhead by 80.5% on average over NVM workloads. When system crashes happen, ShieldNVM’s recovery time is orders of magnitude faster than Osiris. In addition, ShieldNVM also recovers faster than AGIT, which is the Osiris-based state-of-the-art mechanism addressing the recovery time of the secure NVM system. Once the recovery process fails, instead of dropping all data due to malicious attacks, ShieldNVM is able to detect and locate the area of the tampered data with the help of the tracked addresses.

References

  1. Intel. 2015. Intel and Micron Produce Breakthrough Memory Technology: 3D XPoint. Retrieved April 12, 2020 from https://newsroom.intel.com/news-releases/intel-and-micron-produce-breakthrough-memory-technology/.Google ScholarGoogle Scholar
  2. Intel. 2018. Intel Architecture Instruction Set Extensions Programming Reference. https://software.intel.com/sites/default/ files/managed/c5/15/architecture-instruction-set-extensions-programming- reference.pdf.Google ScholarGoogle Scholar
  3. Pmem.io. 2019. Persistent Memory Development Kit. Retrieved April 12, 2020 from https://pmem.io/pmdk/.Google ScholarGoogle Scholar
  4. Mohammad Alshboul, James Tuck, and Yan Solihin. 2018. Lazy persistency: A high-performing and write-efficient software persistency technique. In Proceedings of the 45th Annual International Symposium on Computer Architecture (ISCA’18). IEEE, Los Alamitos, CA, 439--451. DOI:https://doi.org/10.1109/ISCA.2018.00044Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. Amro Awad, Pratyusa Manadhata, Stuart Haber, Yan Solihin, and William Horne. 2016. Silent Shredder: Zero-cost shredding for secure non-volatile main memory controllers. In Proceedings of the 21st International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’16). ACM, New York, NY, 263--276. DOI:https://doi.org/10.1145/2872362.2872377Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. Amro Awad, Mao Ye, Yan Solihin, Laurent Njilla, and Kazi Abu Zubair. 2019. Triad-NVM: Persistency for integrity-protected and encrypted non-volatile memories. In Proceedings of the 46th International Symposium on Computer Architecture (ISCA’19). ACM, New York, NY, 104--115. DOI:https://doi.org/10.1145/3307650.3322250Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. Eduardo B. 2017. Enhancing High-Performance Computing with Persistent Memory Technology. Retrieved April 12, 2020 from https://software.intel.com/en-us/articles/enhancing-high-performance-computing-with-persistent-memory-technology.Google ScholarGoogle Scholar
  8. Nathan Binkert, Bradford Beckmann, Gabriel Black, Steven K. Reinhardt, Ali Saidi, Arkaprava Basu, Joel Hestness, et al. 2011. The Gem5 simulator. SIGARCH Computer Architecture News 39, 2 (Aug. 2011), 1--7. DOI:https://doi.org/10.1145/2024716.2024718Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. Sui Chen, Faen Zhang, Lei Liu, and Lu Peng. 2019. Efficient GPU NVRAM persistence with helper warps. In Proceedings of the 56th Annual Design Automation Conference (DAC’19). ACM, New York, NY, Article 155, 6 pages. DOI:https://doi.org/10.1145/3316781.3317810Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. Youmin Chen, Jiwu Shu, Jiaxin Ou, and Youyou Lu. 2018. HiNFS: A persistent memory file system with both buffering and direct-access. ACM Transactions on Storage 14, 1 (April 2018), Article 4, 30 pages. DOI:https://doi.org/10.1145/3204454Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. S. Chhabra and Y. Solihin. 2011. i-NVMM: A secure non-volatile main memory system with incremental encryption. In Proceedings of the 2011 38th Annual International Symposium on Computer Architecture (ISCA’11). 177--188. DOI:https://doi.org/10.1145/2000064.2000086Google ScholarGoogle Scholar
  12. Joel Coburn, Adrian M. Caulfield, Ameen Akel, Laura M. Grupp, Rajesh K. Gupta, Ranjit Jhala, and Steven Swanson. 2011. NV-Heaps: Making persistent objects fast and safe with next-generation, non-volatile memories. In Proceedings of the 16th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’11). ACM, New York, NY, 105--118. DOI:https://doi.org/10.1145/1950365.1950380Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. Jeremy Condit, Edmund B. Nightingale, Christopher Frost, Engin Ipek, Benjamin Lee, Doug Burger, and Derrick Coetzee. 2009. Better I/O through byte-addressable, persistent memory. In Proceedings of the ACM SIGOPS 22nd Symposium on Operating Systems Principles (SOSP’09). ACM, New York, NY, 133--146. DOI:https://doi.org/10.1145/1629575.1629589Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. Subramanya R. Dulloor, Sanjay Kumar, Anil Keshavamurthy, Philip Lantz, Dheeraj Reddy, Rajesh Sankaran, and Jeff Jackson. 2014. System software for persistent memory. In Proceedings of the 9th European Conference on Computer Systems (EuroSys’14). ACM, New York, NY, Article 15, 15 pages. DOI:https://doi.org/10.1145/2592798.2592814Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. B. Gassend, G. E. Suh, D. Clarke, M. van Dijk, and S. Devadas. 2003. Caches and hash trees for efficient memory integrity verification. In Proceedings of the 9th International Symposium on High-Performance Computer Architecture (HPCA’03). 295--306. DOI:https://doi.org/10.1109/HPCA.2003.1183547Google ScholarGoogle Scholar
  16. Vaibhav Gogte, Stephan Diestelhorst, William Wang, Satish Narayanasamy, Peter M. Chen, and Thomas F. Wenisch. 2018. Persistency for synchronization-free regions. In Proceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI’18). ACM, New York, NY, 46--61. DOI:https://doi.org/10.1145/3192366.3192367Google ScholarGoogle Scholar
  17. Jinyu Gu, Qianqian Yu, Xiayang Wang, Zhaoguo Wang, Binyu Zang, Haibing Guan, and Haibo Chen. 2019. Pisces: A scalable and efficient persistent transactional memory. In Proceedings of the 2019 USENIX Annual Technical Conference (USENIX ATC’19). 913--928. https://www.usenix.org/conference/atc19/presentation/guGoogle ScholarGoogle Scholar
  18. Siddharth Gupta, Alexandros Daglis, and Babak Falsafi. 2019. Distributed logless atomic durability with persistent memory. In Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-52). ACM, New York, NY, 466--478. DOI:https://doi.org/10.1145/3352460.3358321Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. Terry Ching-Hsiang Hsu, Helge Brügner, Indrajit Roy, Kimberly Keeton, and Patrick Eugster. 2017. NVthreads: Practical persistence for multi-threaded applications. In Proceedings of the 12th European Conference on Computer Systems (EuroSys’17). ACM, New York, NY, 468--482. DOI:https://doi.org/10.1145/3064176.3064204Google ScholarGoogle Scholar
  20. Qingda Hu, Jinglei Ren, Anirudh Badam, Jiwu Shu, and Thomas Moscibroda. 2017. Log-structured non-volatile main memory. In Proceedings of the 2017 USENIX Annual Technical Conference (USENIX ATC’17). 703--717. https://www.usenix.org/conference/atc17/technical-sessions/presentation/hu.Google ScholarGoogle Scholar
  21. Deukyeon Hwang, Wook-Hee Kim, Youjip Won, and Beomseok Nam. 2018. Endurable transient inconsistency in byte-addressable persistent B+-tree. In Proceedings of the 16th USENIX Conference on File and Storage Technologies (FAST’18). 187--200. https://www.usenix.org/conference/fast18/presentation/hwang.Google ScholarGoogle Scholar
  22. Joseph Izraelevitz, Terence Kelly, and Aasheesh Kolli. 2016. Failure-atomic persistent memory updates via JUSTDO logging. In Proceedings of the 21st International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’16). ACM, New York, NY, 427--442. DOI:https://doi.org/10.1145/2872362.2872410Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. Arpit Joshi, Vijay Nagarajan, Marcelo Cintra, and Stratis Viglas. 2015. Efficient persist barriers for multicores. In Proceedings of the 48th International Symposium on Microarchitecture (MICRO-48). ACM, New York, NY, 660--671. DOI:https://doi.org/10.1145/2830772.2830805Google ScholarGoogle ScholarDigital LibraryDigital Library
  24. A. Joshi, V. Nagarajan, M. Cintra, and S. Viglas. 2018. DHTM: Durable hardware transactional memory. In Proceedings of the 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA’18). 452--465. DOI:https://doi.org/10.1109/ISCA.2018.00045Google ScholarGoogle ScholarDigital LibraryDigital Library
  25. A. Joshi, V. Nagarajan, S. Viglas, and M. Cintra. 2017. ATOM: Atomic durability in non-volatile memory through hardware logging. In Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA’17). 361--372. DOI:https://doi.org/10.1109/HPCA.2017.50Google ScholarGoogle ScholarCross RefCross Ref
  26. Aasheesh Kolli, Vaibhav Gogte, Ali Saidi, Stephan Diestelhorst, Peter M. Chen, Satish Narayanasamy, and Thomas F. Wenisch. 2017. Language-level persistency. In Proceedings of the 44th Annual International Symposium on Computer Architecture (ISCA’17). ACM, New York, NY, 481--493. DOI:https://doi.org/10.1145/3079856.3080229Google ScholarGoogle Scholar
  27. Aasheesh Kolli, Steven Pelley, Ali Saidi, Peter M. Chen, and Thomas F. Wenisch. 2016. High-performance transactions for persistent memories. In Proceedings of the 21st International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’16). ACM, New York, NY, 399--411. DOI:https://doi.org/10.1145/2872362.2872381Google ScholarGoogle Scholar
  28. Aasheesh Kolli, Jeff Rosen, Stephan Diestelhorst, Ali Saidi, Steven Pelley, Sihang Liu, Peter M. Chen, and Thomas F. Wenisch. 2016. Delegated persist ordering. In Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-49). IEEE, Los Alamitos, CA, Article 58, 13 pages. http://dl.acm.org/citation.cfm?id=3195638.3195709.Google ScholarGoogle Scholar
  29. Emre Kultursay, Mahmut Kandemir, Anand Sivasubramaniam, and Onur Mutlu. 2013. Evaluating STT-RAM as an energy-efficient main memory alternative. In Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS’13). 256--267. DOI:https://doi.org/10.1109/ISPASS.2013.6557176Google ScholarGoogle ScholarCross RefCross Ref
  30. Benjamin C. Lee, Engin Ipek, Onur Mutlu, and Doug Burger. 2009. Architecting phase change memory as a scalable DRAM alternative. In Proceedings of the 36th Annual International Symposium on Computer Architecture (ISCA’09). ACM, New York, NY, 2--13. DOI:https://doi.org/10.1145/1555754.1555758Google ScholarGoogle ScholarDigital LibraryDigital Library
  31. J. Lee, T. Kim, and J. Huh. 2016. Reducing the memory bandwidth overheads of hardware security support for multi-core processors. IEEE Transactions on Computers 65, 11 (Nov. 2016), 3384--3397. DOI:https://doi.org/10.1109/TC.2016.2538218Google ScholarGoogle ScholarDigital LibraryDigital Library
  32. T. S. Lehman, A. D. Hilton, and B. C. Lee. 2016. PoisonIvy: Safe speculation for secure memory. In Proceedings of the 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-49). 1--13. DOI:https://doi.org/10.1109/MICRO.2016.7783741Google ScholarGoogle ScholarCross RefCross Ref
  33. Mengxing Liu, Mingxing Zhang, Kang Chen, Xuehai Qian, Yongwei Wu, Weimin Zheng, and Jinglei Ren. 2017. DudeTM: Building durable transactions with decoupling for persistent memory. In Proceedings of the 22nd International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’17). 329--343. DOI:https://doi.org/10.1145/3037697.3037714Google ScholarGoogle ScholarDigital LibraryDigital Library
  34. S. Liu, A. Kolli, J. Ren, and S. Khan. 2018. Crash consistency in encrypted non-volatile main memory systems. In Proceedings of the 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA’18). 310--323. DOI:https://doi.org/10.1109/HPCA.2018.00035Google ScholarGoogle ScholarCross RefCross Ref
  35. Sihang Liu, Korakit Seemakhupt, Gennady Pekhimenko, Aasheesh Kolli, and Samira Khan. 2019. Janus: Optimizing memory and storage support for non-volatile memory systems. In Proceedings of the 46th International Symposium on Computer Architecture (ISCA’19). ACM, New York, NY, 143--156. DOI:https://doi.org/10.1145/3307650.3322206Google ScholarGoogle ScholarDigital LibraryDigital Library
  36. Y. Lu, J. Shu, and L. Sun. 2015. Blurred persistence in transactional persistent memory. In Proceedings of the 2015 31st Symposium on Mass Storage Systems and Technologies (MSST’15). 1--13. DOI:https://doi.org/10.1109/MSST.2015.7208274Google ScholarGoogle ScholarCross RefCross Ref
  37. Y. Lu, J. Shu, L. Sun, and O. Mutlu. 2014. Loose-ordering consistency for persistent memory. In Proceedings of the 2014 IEEE 32nd International Conference on Computer Design (ICCD’14). 216--223. DOI:https://doi.org/10.1109/ICCD.2014.6974684Google ScholarGoogle Scholar
  38. H. Mao, X. Zhang, G. Sun, and J. Shu. 2017. Protect non-volatile memory from wear-out attack based on timing difference of row buffer hit/miss. In Proceedings of the Design, Automation, and Test in Europe Conference and Exhibition (DATE’17). 1623--1626. DOI:https://doi.org/10.23919/DATE.2017.7927251Google ScholarGoogle Scholar
  39. David Mulnix. 2015. Intel Xeon Processor D Product Family Technical Overview. Retrieved April 12, 2020 from https://software.intel.com/en-us/articles/intel-xeon-processor-d-product-family-technical-overview#_Toc419802876y.Google ScholarGoogle Scholar
  40. Sanketh Nalli, Swapnil Haria, Mark D. Hill, Michael M. Swift, Haris Volos, and Kimberly Keeton. 2017. An analysis of persistent memory use with WHISPER. In Proceedings of the 22nd International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’17). ACM, New York, NY, 135--148. DOI:https://doi.org/10.1145/3037697.3037730Google ScholarGoogle ScholarDigital LibraryDigital Library
  41. Moohyeon Nam, Hokeun Cha, Young Ri Choi, Sam H. Noh, and Beomseok Nam. 2019. Write-optimized dynamic hashing for persistent memory. In Proceedings of the 17th USENIX Conference on File and Storage Technologies (FAST’19). 31--44. https://www.usenix.org/conference/fast19/presentation/nam.Google ScholarGoogle ScholarDigital LibraryDigital Library
  42. Dushyanth Narayanan and Orion Hodson. 2012. Whole-system persistence. In Proceedings of the 17th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’12). ACM, New York, NY, 401--410. DOI:https://doi.org/10.1145/2150976.2151018Google ScholarGoogle ScholarDigital LibraryDigital Library
  43. Yuanjiang Ni, Jishen Zhao, Daniel Bittman, and Ethan Miller. 2018. Reducing NVM writes with optimized shadow paging. In Proceedings of the 10th USENIX Workshop on Hot Topics in Storage and File Systems (HotStorage’18). https://www.usenix.org/conference/hotstorage18/presentation/ni.Google ScholarGoogle ScholarDigital LibraryDigital Library
  44. Ismail Oukid, Johan Lasperas, Anisoara Nica, Thomas Willhalm, and Wolfgang Lehner. 2016. FPTree: A hybrid SCM-DRAM persistent and concurrent B-tree for storage class memory. In Proceedings of the 2016 International Conference on Management of Data (SIGMOD’16). ACM, New York, NY, 371--386. DOI:https://doi.org/10.1145/2882903.2915251Google ScholarGoogle ScholarDigital LibraryDigital Library
  45. Steven Pelley, Peter M. Chen, and Thomas F. Wenisch. 2014. Memory persistency. In Proceedings of the 41st Annual International Symposium on Computer Architecuture (ISCA’14). IEEE, Los Alamitos, CA, 265--276. http://dl.acm.org/citation.cfm?id=2665671.2665712.Google ScholarGoogle ScholarDigital LibraryDigital Library
  46. Joydeep Rakshit and Kartik Mohanram. 2017. ASSURE: Authentication scheme for SecURE energy efficient non-volatile memories. In Proceedings of the 54th Annual Design Automation Conference (DAC’17). ACM, New York, NY, Article 11, 6 pages. DOI:https://doi.org/10.1145/3061639.3062205Google ScholarGoogle ScholarDigital LibraryDigital Library
  47. Pedro Ramalhete, Andreia Correia, Pascal Felber, and Nachshon Cohen. 2019. OneFile: A wait-free persistent transactional memory. In Proceedings of the 49th IEEE/IFIP International Conference on Dependable Systems and Networks (DSN’19). 151--163. DOI:https://doi.org/10.1109/DSN.2019.00028Google ScholarGoogle ScholarCross RefCross Ref
  48. Jinglei Ren, Jishen Zhao, Samira Khan, Jongmoo Choi, Yongwei Wu, and Onur Mutlu. 2015. ThyNVM: Enabling software-transparent crash consistency in persistent memory systems. In Proceedings of the 48th International Symposium on Microarchitecture (MICRO-48). ACM, New York, NY, 672--685. DOI:https://doi.org/10.1145/2830772.2830802Google ScholarGoogle ScholarDigital LibraryDigital Library
  49. B. Rogers, S. Chhabra, M. Prvulovic, and Y. Solihin. 2007. Using address independent seed encryption and Bonsai Merkle Trees to make secure processors OS- and performance-friendly. In Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40). 183--196. DOI:https://doi.org/10.1109/MICRO.2007.16Google ScholarGoogle ScholarCross RefCross Ref
  50. A. M. Rudoff. 2016. Deprecating the PCOMMIT Instruction. Retrieved April 12, 2020 from https://software.intel.com/en-us/blogs/2016/09/12/deprecate-pcommit-instruction.Google ScholarGoogle Scholar
  51. G. Saileshwar, P. Nair, P. Ramrakhyani, W. Elsasser, J. Joao, and M. Qureshi. 2018. Morphable counters: Enabling compact integrity trees for low-overhead secure memories. In Proceedings of the 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-51). 416--427. DOI:https://doi.org/10.1109/MICRO.2018.00041Google ScholarGoogle ScholarDigital LibraryDigital Library
  52. G. Saileshwar, P. J. Nair, P. Ramrakhyani, W. Elsasser, and M. K. Qureshi. 2018. SYNERGY: Rethinking secure-memory design for error-correcting memories. In Proceedings of the 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA’18). 454--465. DOI:https://doi.org/10.1109/HPCA.2018.00046Google ScholarGoogle ScholarCross RefCross Ref
  53. S. Shin, S. K. Tirukkovalluri, J. Tuck, and Y. Solihin. 2017. Proteus: A flexible and fast software supported hardware logging approach for NVM. In Proceedings of the 2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-50). 178--190.Google ScholarGoogle Scholar
  54. T. Silbergleit Lehman, A. D. Hilton, and B. C. Lee. 2018. MAPS: Understanding metadata access patterns in secure memory. In Proceedings of the 2018 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS’18). 33--43. DOI:https://doi.org/10.1109/ISPASS.2018.00012Google ScholarGoogle ScholarCross RefCross Ref
  55. G. E. Suh, D. Clarke, B. Gasend, M. van Dijk, and S. Devadas. 2003. Efficient memory integrity verification and encryption for secure processors. In Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-36). 339--350. DOI:https://doi.org/10.1109/MICRO.2003.1253207Google ScholarGoogle Scholar
  56. S. Swami and K. Mohanram. 2017. COVERT: Counter OVErflow ReducTion for efficient encryption of non-volatlle memories. In Proceedings of the Design, Automation, and Test in Europe Conference and Exhibition (DATE’17). 906--909. DOI:https://doi.org/10.23919/DATE.2017.7927117Google ScholarGoogle Scholar
  57. Shivam Swami and Kartik Mohanram. 2018. ACME: Advanced counter mode encryption for secure non-volatile memories. In Proceedings of the 55th Annual Design Automation Conference (DAC’18). ACM, New York, NY, Article 86, 6 pages. DOI:https://doi.org/10.1145/3195970.3195983Google ScholarGoogle ScholarDigital LibraryDigital Library
  58. S. Swami and K. Mohanram. 2018. ARSENAL: Architecture for secure non-volatile memories. IEEE Computer Architecture Letters 17, 2 (July 2018), 192--196. DOI:https://doi.org/10.1109/LCA.2018.2863281Google ScholarGoogle ScholarCross RefCross Ref
  59. S. Swami, J. Rakshit, and K. Mohanram. 2016. SECRET: Smartly EnCRypted energy efficienT non-volatile memories. In Proceedings of the 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC’16). 1--6. DOI:https://doi.org/10.1145/2897937.2898087Google ScholarGoogle Scholar
  60. Shivam Swami, Joydeep Rakshit, and Kartik Mohanram. 2018. STASH: Security architecture for smart hybrid memories. In Proceedings of the 55th Annual Design Automation Conference (DAC’18). ACM, New York, NY, Article 85, 6 pages. DOI:https://doi.org/10.1145/3195970.3196123Google ScholarGoogle ScholarDigital LibraryDigital Library
  61. Meysam Taassori, Ali Shafiee, and Rajeev Balasubramonian. 2018. VAULT: Reducing paging overheads in SGX with efficient integrity verification structures. ACM SIGPLAN Notices 53 (March 2018), 665--678. DOI:https://doi.org/10.1145/3296957.3177155Google ScholarGoogle ScholarDigital LibraryDigital Library
  62. Haris Volos, Andres Jaan Tack, and Michael M. Swift. 2011. Mnemosyne: Lightweight persistent memory. In Proceedings of the 16th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’11). ACM, New York, NY, 91--104. DOI:https://doi.org/10.1145/1950365.1950379Google ScholarGoogle Scholar
  63. X. Wu and A. L. N. Reddy. 2011. SCMFS: A file system for storage class memory. In Proceedings of 2011 International Conference for High Performance Computing, Networking, Storage, and Analysis (SC’11). 1--11.Google ScholarGoogle ScholarDigital LibraryDigital Library
  64. Jian Xu and Steven Swanson. 2016. NOVA: A log-structured file system for hybrid volatile/non-volatile main memories. In Proceedings of the 14th USENIX Conference on File and Storage Technologies (FAST’16). 323--338. https://www.usenix.org/conference/fast16/technical-sessions/presentation/xu.Google ScholarGoogle ScholarDigital LibraryDigital Library
  65. Chenyu Yan, Daniel Englender, Milos Prvulovic, Brian Rogers, and Yan Solihin. 2006. Improving cost, performance, and security of memory encryption and authentication. In Proceedings of the 33rd Annual International Symposium on Computer Architecture (ISCA’06). IEEE, Los Alamitos, CA, 179--190. DOI:https://doi.org/10.1109/ISCA.2006.22Google ScholarGoogle ScholarDigital LibraryDigital Library
  66. Fan Yang, Youyou Lu, Youmin Chen, Haiyu Mao, and Jiwu Shu. 2019. No compromises: Secure NVM with crash consistency, write-efficiency and high-performance. In Proceedings of the 56th Annual Design Automation Conference (DAC’19). 1--6. DOI:https://doi.org/10.1145/3316781.3317869Google ScholarGoogle ScholarDigital LibraryDigital Library
  67. Mao Ye. 2018. Osiris: A low-cost mechanism to enable restoration of secure non-volatile memories. In Proceedings of the 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-51).Google ScholarGoogle ScholarDigital LibraryDigital Library
  68. Vinson Young, Prashant J. Nair, and Moinuddin K. Qureshi. 2015. DEUCE: Write-efficient encryption for non-volatile memories. In Proceedings of the 20th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’15). ACM, New York, NY, 33--44. DOI:https://doi.org/10.1145/2694344.2694387Google ScholarGoogle Scholar
  69. J. Zhao, S. Li, D. H. Yoon, Y. Xie, and N. P. Jouppi. 2013. Kiln: Closing the performance gap between systems with and without persistence support. In Proceedings of the 2013 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-46). 421--432.Google ScholarGoogle Scholar
  70. Kazi Abu Zubair and Amro Awad. 2019. Anubis: Ultra-low overhead and recovery time for secure non-volatile memories. In Proceedings of the 46th International Symposium on Computer Architecture (ISCA’19). ACM, New York, NY, 157--168. DOI:https://doi.org/10.1145/3307650.3322252Google ScholarGoogle ScholarDigital LibraryDigital Library
  71. Pengfei Zuo, Yu Hua, and Jie Wu. 2018. Write-optimized and high-performance hashing index scheme for persistent memory. In Proceedings of the 13th USENIX Symposium on Operating Systems Design and Implementation (OSDI’18). 461--476. https://www.usenix.org/conference/osdi18/presentation/zuo.Google ScholarGoogle Scholar
  72. Pengfei Zuo, Yu Hua, and Yuan Xie. 2019. SuperMem: Enabling application-transparent secure persistent memory with low overheads. In Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-52). ACM, New York, NY, 479--492. DOI:https://doi.org/10.1145/3352460.3358290Google ScholarGoogle ScholarDigital LibraryDigital Library

Index Terms

  1. ShieldNVM: An Efficient and Fast Recoverable System for Secure Non-Volatile Memory

            Recommendations

            Comments

            Login options

            Check if you have access through your login credentials or your institution to get full access on this article.

            Sign in

            Full Access

            • Published in

              cover image ACM Transactions on Storage
              ACM Transactions on Storage  Volume 16, Issue 2
              SOSP 2019 Special Section and Regular Papers
              May 2020
              194 pages
              ISSN:1553-3077
              EISSN:1553-3093
              DOI:10.1145/3399155
              • Editor:
              • Sam H. Noh
              Issue’s Table of Contents

              Copyright © 2020 ACM

              Publisher

              Association for Computing Machinery

              New York, NY, United States

              Publication History

              • Published: 18 May 2020
              • Online AM: 7 May 2020
              • Accepted: 1 February 2020
              • Revised: 1 December 2019
              • Received: 1 September 2019
              Published in tos Volume 16, Issue 2

              Permissions

              Request permissions about this article.

              Request Permissions

              Check for updates

              Qualifiers

              • research-article
              • Research
              • Refereed

            PDF Format

            View or Download as a PDF file.

            PDF

            eReader

            View online with eReader.

            eReader

            HTML Format

            View this article in HTML Format .

            View HTML Format
            About Cookies On This Site

            We use cookies to ensure that we give you the best experience on our website.

            Learn more

            Got it!