Proceedings of the 18th annual international symposium on Computer architecture

ISCA '91: Proceedings of the 18th annual international symposium on Computer architecture

April 1991

1991 Proceeding

Chairman:
Zvonko Vranesic

Publisher:

Association for Computing Machinery
New York
NY
United States

Conference:

ISCA91: 18th International Symposium on Computer Architecture Toronto Ontario Canada May 27 - 30, 1991

ISBN:

978-0-89791-394-2

Published:

01 April 1991

Sponsors:

SIGARCH, IEEE-CS

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ISCA '24

Sponsor:
sigarch

ISCA '24: The 51st Annual International Symposium on Computer Architecture

June 29 - July 3, 2024

Buenos Aires , Argentina

ISCA '24 website

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Citation count

1,796

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403

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2,299

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23,226

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ISCA '91: Proceedings of the 18th annual international symposium on Computer architecture

1991

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The SNAP-1 parallel AI prototype

R. F. DeMara,
D. I. Moldovan

pp 2–11https://doi.org/10.1145/115952.115954

- 9
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GT-EP: a novel high-performance real-time architecture

Wei Siong Tan,
H. Russ,
Cecil O. Alford

pp 13–21https://doi.org/10.1145/115952.115955

- 0
- 361
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IXM2: a parallel associative processor

Tetsuya Higuchi,
Tatsumi Furuya,
Kenichi Handa,
Naoto Takahashi,
Hiroyasu Nishiyama,
Akio Kokubu

pp 22–31https://doi.org/10.1145/115952.115956

- 6
- 337
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Total Downloads337
Last 12 Months25
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Branch history table prediction of moving target branches due to subroutine returns

David R. Kaeli,
Philip G. Emma

pp 34–42https://doi.org/10.1145/115952.115957

- 81
- 1,140
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Last 12 Months142
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An architecture for software-controlled data prefetching

Alexander C. Klaiber,
Henry M. Levy

pp 43–53https://doi.org/10.1145/115952.115958

- 161
- 762
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Total Downloads762
Last 12 Months65
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Data prefetching in multiprocessor vector cache memories

John W. C. Fu,
Janak H. Patel

pp 54–63https://doi.org/10.1145/115952.115959

- 121
- 740
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Total Downloads740
Last 12 Months58
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Reducing memory contention in shared memory multiprocessors

D. T. Harper

pp 66–73https://doi.org/10.1145/115952.115960

- 1
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Total Downloads394
Last 12 Months31
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Pseudo-randomly interleaved memory

B. Ramakrishna Rau

pp 74–83https://doi.org/10.1145/115952.115961

- 81
- 1,545
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Total Downloads1,545
Last 12 Months342
Last 6 weeks45

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Evaluation of memory system extensions

Kai Li,
Karin Petersen

pp 84–93https://doi.org/10.1145/115952.115962

- 27
- 424
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Last 12 Months25
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High performance interprocessor communication through optical wavelength division multiple access channels

Patrick W. Dowd

pp 96–105https://doi.org/10.1145/115952.115963

- 21
- 496
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Total Downloads496
Last 12 Months33
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Race-free interconnection networks and multiprocessor consistency

Anders Landin,
Erik Hagersten,
Seif Haridi

pp 106–115https://doi.org/10.1145/115952.115964

- 39
- 491
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Total Downloads491
Last 12 Months40
Last 6 weeks15

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Deadlock-free multicast wormhole routing in multicomputer networks

Xiaola Lin,
Lionel M. Ni

pp 116–125https://doi.org/10.1145/115952.115965

- 76
- 1,419
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Total Downloads1,419
Last 12 Months45
Last 6 weeks6

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Dynamic base register caching: a technique for reducing address bus width

Matthew Farrens,
Arvin Park

pp 128–137https://doi.org/10.1145/115952.115966

- 63
- 446
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Total Downloads446
Last 12 Months35
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Implementing a cache for a high-performance GaAs microprocessor

O. A. Olukotun,
T. N. Mudge,
R. B. Brown

pp 138–147https://doi.org/10.1145/115952.115967

- 12
- 341
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Total Downloads341
Last 12 Months30
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Classification and performance evaluation of instruction buffering techniques

Lizyamma Kurian,
Paul T. Hulina,
Lee D. Coraor,
Dhamir N. Mannai

pp 150–159https://doi.org/10.1145/115952.115968

- 4
- 376
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Total Downloads376
Last 12 Months35
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OHMEGA: a VLSI superscalar processor architecture for numerical applications

Masaitsu Nakajima,
Hiraku Nakano,
Yasuhiro Nakakura,
Tadahiro Yoshida,
Yoshiyuki Goi,
Yuji Nakai,
Reiji Segawa,
Takeshi Kishida,
Hiroshi Kadota

pp 160–168https://doi.org/10.1145/115952.115969

- 5
- 324
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Total Downloads324
Last 12 Months25
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An empirical study of the CRAY Y-MP processor using the Perfect club benchmarks

Sriram Vajapeyam,
Gurindar S. Sohi,
Wei-Chung Hsu

pp 170–179https://doi.org/10.1145/115952.115970

- 7
- 392
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Total Downloads392
Last 12 Months51
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Instruction level profiling and evaluation of the IBM/6000

Chriss Stephens,
Bryce Cogswell,
John Heinlein,
Gregory Palmer,
John P. Shen

pp 180–189https://doi.org/10.1145/115952.115971

- 30
- 381
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Last 12 Months36
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Performance prediction and tuning on a multiprocessor

R. T. Dimpsey,
R. K. Iyer

pp 190–199https://doi.org/10.1145/115952.115972

- 9
- 332
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Performance evaluation of a communication system for transputer-networks based on monitored event traces

C. W. Oehlrich,
A. Quick

pp 202–211https://doi.org/10.1145/115952.115973

- 3
- 321
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Total Downloads321
Last 12 Months30
Last 6 weeks1

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Chaos router: architecture and performance

S. Konstantinidou,
L. Snyder

pp 212–221https://doi.org/10.1145/115952.115974

- 56
- 612
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Total Downloads612
Last 12 Months57
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Scheduling pipelined communication in distributed memory multiprocessors for real-time applications

Shridhar B. Shukla,
Dharma P. Agrawal

pp 222–231https://doi.org/10.1145/115952.115975

- 19
- 297
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Total Downloads297
Last 12 Months17
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Detecting data races on weak memory systems

Sarita V. Adve,
Mark D. Hill,
Barton P. Miller,
Robert H. B. Netzer

pp 234–243https://doi.org/10.1145/115952.115976

- 131
- 724
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Total Downloads724
Last 12 Months59
Last 6 weeks8

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On the validity of trace-driven simulation for multiprocessors

Eric J. Koldinger,
Susan J. Eggers,
Henry M. Levy

pp 244–253https://doi.org/10.1145/115952.115977

- 29
- 419
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Total Downloads419
Last 12 Months29
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Comparative evaluation of latency reducing and tolerating techniques

Anoop Gupta,
John Hennessy,
Kourosh Gharachorloo,
Todd Mowry,
Wolf-Dietrich Weber

pp 254–263https://doi.org/10.1145/115952.115978

- 156
- 1,166
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Total Downloads1,166
Last 12 Months83
Last 6 weeks20

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IMPACT: an architectural framework for multiple-instruction-issue processors

Pohua P. Chang,
Scott A. Mahlke,
William Y. Chen,
Nancy J. Warter,
Wen-mei W. Hwu

pp 266–275https://doi.org/10.1145/115952.115979

- 237
- 1,003
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Total Downloads1,003
Last 12 Months78
Last 6 weeks9

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Single instruction stream parallelism is greater than two

Michael Butler,
Tse-Yu Yeh,
Yale Patt,
Mitch Alsup,
Hunter Scales,
Michael Shebanow

pp 276–286https://doi.org/10.1145/115952.115980

- 152
- 1,531
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Total Downloads1,531
Last 12 Months234
Last 6 weeks51

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Exploiting fine-grained parallelism through a combination of hardware and software techniques

Stephen Melvin,
Yale Patt

pp 287–296https://doi.org/10.1145/115952.115981

- 38
- 577
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Total Downloads577
Last 12 Months51
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Comparison of hardware and software cache coherence schemes

Sarita V. Adve,
Vikram S. Adve,
Mark D. Hill,
Mary K. Vernon

pp 298–308https://doi.org/10.1145/115952.115982

- 52
- 1,027
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Total Downloads1,027
Last 12 Months167
Last 6 weeks39

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Modeling the performance of limited pointers directories for cache coherence

Richard Simoni,
Mark Horowitz

pp 309–319https://doi.org/10.1145/115952.115983

- 10
- 358
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Total Downloads358
Last 12 Months37
Last 6 weeks8

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Contributors

Zvonko G Vranesic
University of Toronto
- Publication Years1970 - 2013
- Publication counts57
- Citation count887
- Available for Download20
- Downloads (cumulative)8,352
- Downloads (12 months)534
- Downloads (6 weeks)82
- Average Downloads per Article418
- Average Citation per Article16
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Index Terms

Proceedings of the 18th annual international symposium on Computer architecture

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Acceptance Rates

Overall Acceptance Rate543of3,203submissions,17%

Year	Submitted	Accepted	Rate
ISCA '22	400	67	17%
ISCA '19	365	62	17%
ISCA '17	322	54	17%
ISCA '13	288	56	19%
ISCA '12	262	47	18%
ISCA '08	259	37	14%
ISCA '06	234	31	13%
ISCA '05	194	45	23%
ISCA '04	217	31	14%
ISCA '03	184	36	20%
ISCA '02	180	27	15%
ISCA '01	163	24	15%
ISCA '99	135	26	19%
Overall	3,203	543	17%

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Index Terms

Proceedings of the 18th annual international symposium on Computer architecture

Recommendations

CompSysTech '17: Proceedings of the 18th International Conference on Computer Systems and Technologies

COMAD '12: Proceedings of the 18th International Conference on Management of Data

CSL-LICS '14: Proceedings of the Joint Meeting of the Twenty-Third EACSL Annual Conference on Computer Science Logic (CSL) and the Twenty-Ninth Annual ACM/IEEE Symposium on Logic in Computer Science (LICS)

Acceptance Rates