2011 Proceeding- General Chairs:
- José Flich,
- Davide Bertozzi,
- Program Chairs:
- Tor Skeie,
- Daniele Ludovici
The papers in this volume form the proceedings of the 5th Interconnection Network Architecture: On-Chip, Multi-Chip (INAOCMC) Workshop held on January 23rd, 2011, in conjunction with the 6th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC), January 2426, 2011, Heraklion, Creete, Greece.
The main goal of the INAOCMC Workshop is to provide a focused forum for researchers to present and discuss innovative ideas and solutions in the field of on-chip, multi-chip interconnection network architecture. The workshop aims at bringing together researchers and engineers from industry and academia to share ideas and thoughts about networking of devices in both the off-chip and the on-chip environment, each with its own design constraints. Interestingly, this year the workshop is organized in two sessions embracing such aspects and a further session tackling emerging technologies which is also the focus of our exciting keynote speech.
Paper submissions were received from 12 countries spread all over the world and all the papers were reviewed by four committee members. The deliberation has been conducted by the Program Committee electronically. The Program Committee selected 8 papers for presentation at the Workshop. The papers were judged based on originality, quality and relevance to the subject area of the Workshop. In addition to the 8 regular papers, the program of the workshop has been enriched by a keynote talk by Professor Luca Carloni, Columbia University, NY, USA. Finally, selected papers will be invited for submission and possible contribution to a special issue of the ACM Transactions on Embedded Computing Systems (TECS).
Proceeding Downloads
Emerging silicon photonics technologies for multi-core platform architectures
The integration of emerging silicon photonics technologies with CMOS processes offers important advantages for the realization of scalable interconnection networks for both intra-chip and off-chip communication in next-generation multi-core computing ...
EEEP: an extreme end to end flow control protocol for SDRAM access through networks on chip
MPSoC platforms face an increasing diversity of traffic requirements due to the interaction between cores. This interaction is driven by the applications run by the user, and leads to the coexistence of the best effort traffic and the guaranteed service ...
An improved algorithm for slot selection in the Æthereal network-on-chip
The rapid development in the electronics industry leads to a design process dominated by time-to-market constraints. The balance is shifted from logic design to packaging of already existing IP which results in a search for solutions for interconnecting ...
iFDOR: dynamic rerouting on-chip
Many-core chip design requires flexible routing solutions for the interconnect to handle faults, provide performance partitions, and react to dynamic changes in processing requirements and power/heat distribution. We have developed a logic based ...
Process scheduling for future multicore processors
In this paper, we study and analyze process scheduling problems for future multicore processors. It is expected that hundreds or even thousands of cores will be integrated on a single chip, known as a Chip Multiprocessor (CMP). However, operating system ...
Switch allocator for bufferless network-on-chip routers
Bufferless switches can be an attractive and energy-efficient design option for on-chip networks when network utilization is low and low-latency operation matters the most. However, this promising design option is limited by the complexity of the ...
A power-efficient network on-chip topology
NoCs have become a critical component in many-core architectures. Usually, the preferred topology is the 2D-Mesh as it enables a tile-based layout significantly reducing the design effort. However, new emerging challenges such as power consumption need ...
Mesochronous NoC technology for power-efficient GALS MPSoCs
MPSoCs are today frequently designed as the composition of multiple voltage/frequency islands, thus calling for a GALS clocking style. In this context, the on-chip interconnection network can be either inferred as a single and independent clock domain ...
Abstract modelling of switching elements for optical networks-on-chip with technology platform awareness
This paper reports the lessons learned in the abstraction process of the behaviour of switching elements for optical networks-on-chip, resulting in technology-annotated abstract models for the SystemC modelling and simulation environment. The paper ...
Index Terms
Proceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip
Recommendations
Acceptance Rates
| Year | Submitted | Accepted | Rate |
|---|---|---|---|
| INA-OCMC '14 | 10 | 5 | 50% |
| IMA-OCMC '13 | 17 | 7 | 41% |
| Overall | 27 | 12 | 44% |