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HLPP '11: Proceedings of the fifth international workshop on High-level parallel programming and applications
ACM2011 Proceeding
Publisher:
  • Association for Computing Machinery
  • New York
  • NY
  • United States
Conference:
ICFP '11: ACM SIGPLAN International Conference on Functional Programming Tokyo Japan 18 September 2011
ISBN:
978-1-4503-0862-5
Published:
18 September 2011
Sponsors:
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Abstract

It is our great pleasure to welcome you to the 5th ACM SIGPLAN Workshop on High-Level Parallel Programming and Applications --HLPP 2011.

As processor and system manufacturers adjust their roadmaps towards increasing levels of both inter- and intra-chip parallelism, so the urgency of reorienting the mainstream software industry towards these architectures grows. At present, popular parallel and distributed programming methodologies are dominated by low-level techniques such as send/receive message passing or equivalently unstructured shared memory mechanisms. Higher-level, structured approaches offer many possible advantages and have a key role to play in the scalable exploitation of ubiquitous parallelism.

HLPP 2011 is the fifth in a series of workshops seeking to provide a forum for discussion and research about such high-level approaches to parallel programming.

The call for papers generated 7 submissions, from which the Program Committee selected 4 papers for inclusion in the final workshop program. In addition to the refereed papers, the final program includes an invited talk by Takahiro Katagiri (University of Tokyo, Japan).

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SESSION: Invited talk
invited-talk
Towards auto-tuning description language to heterogeneous computing environment

Computer architectures are becoming more and more complex due to non-standardized memory accesses and hierarchical caches. It is very difficult for scientists and engineers to optimize their code to extract potential performance improvements on these ...

SESSION: Skeletal parallelism & algorithm
research-article
Cache size in a cost model for heterogeneous skeletons

High performance architectures are increasingly heterogeneous with shared and distributed memory components. Programming such architectures is complicated and performance portability is a major issue as the architectures evolve.

This paper proposes a ...

research-article
An efficient skew-insensitive algorithm for join processing on grid architectures

Scientific experiments in many domains generate a huge amount of data whose size is in the range of hundreds of megabytes to petabytes. These data are stored on geographically distributed and heterogeneous resources. Researchers who need to analyze and ...

SESSION: Formal analysis & type system
research-article
Formally specifying and analyzing a parallel virtual machine for lazy functional languages using Maude

Pure lazy functional languages are a promising programming paradigm for harvesting massive parallelism, as their abstraction features and lack of side effects support the development of modular programs without unneeded serialization. We give a new ...

research-article
Type system for a safe execution of parallel programs in BSML

BSML, or Bulk Synchronous Parallel ML, is a high-level language based on ML and dedicated to parallel computation. In this paper, an extended type system that guarantees the safety of parallel programs is presented. It prevents non-determinism and ...

Contributors
  • Kochi University of Technology

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