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A practical methodology to validate the statistical behavior of bloom filters
Bloom filters are commonly used to test for set membership. A Bloom filter consists of a series of hash functions, whose combined signature is used to construct a composite hash. Applications are broad, and include networking, transactional memory, ...
Scalable and realistic benchmark synthesis for efficient NoC performance evaluation: a complex network analysis approach
The complexity of the design-space exploration of large-scale NoCs is exacerbated not only by the ever-increasing number of cores, but also by the increased runtime uncertainties in both the scale and task structure of the emerging applications. ...
An accurate and flexible early memory system power evaluation approach using a microcomponent method
As energy efficiency has become a primary concern, system designers have greater need for a flexible and highly accurate power estimation method for evaluating different architecture options. Since memory is an increasingly dominant power consumer, we ...
Time in cyber-physical systems
- Aviral Shrivastava,
- Patricia Derler,
- Ya-Shian Li Baboud,
- Kevin Stanton,
- Mohammad Khayatian,
- Hugo A. Andrade,
- Marc Weiss,
- John Eidson,
- Sundeep Chandhoke
Many modern cyber-physical systems (CPS), especially industrial automation systems, require the actions of multiple computational systems to be performed at much higher rates and more tightly synchronized than is possible with ad hoc designs. Time is ...
A design to reduce write amplification in object-based NAND flash devices
Write amplification is a major cause of performance and endurance degradations in NAND flash based storage systems. In an object-based NAND flash device, two causes of write amplification are onode partial update and cascading update. Updating one onode,...
How to enable software isolation and boost system performance with sub-block erase over 3D flash memory
The write amplification problem deteriorates as the block size of modern flash-memory chips keeps increasing. Without the careful garbage collection, significant live-page copying might even worsen the reliability problem, that is already severe to 3D ...
Realizing erase-free SLC flash memory with rewritable programming design
Over the past years, the adaptation of flash memory has seen a tremendous growth in a wide range of fields, with high-end applications demanding ever higher reliability and performance for storage devices. Even though a single-level-cell (SLC) flash ...
IoT technologies for embedded computing: a survey
Emergence of Internet-of-Things brings a whole new class of applications and higher efficiency for existing services. Application-specific requirements, as well as connectivity and communication ability of devices have introduced new challenges for IoT ...
Distributed QoS management for internet of things under resource constraints
Internet-of-Things (IoT) envisions an infrastructure of ubiquitous networked smart devices offering advanced monitoring and control services. Current art in IoT architectures utilizes gateways to enable application-specific connectivity to IoT devices. ...
Evolving authentication design considerations for the internet of biometric things (IoBT)
The Internet of Things (IoT) is a design implementation of embedded system design that connects a variety of devices, sensors, and physical objects to a larger connected network (e.g. the Internet) which requires human-to-human or human-to-computer ...
Fast and cycle-accurate simulation of multi-threaded applications on SMP architectures using hybrid prototyping
This paper presents a fast and cycle accurate simulation environment for early power-performance analysis of multithreaded applications targeted to symmetric multiprocessing embedded architectures. Our simulation environment leverages the hybrid ...
Efficient design space exploration by knowledge transfer
Due to the exponentially increasing size of design space of microprocessors and time-consuming simulations, predictive models have been widely employed in design space exploration (DSE). Traditional approaches mostly build a program-specific predictor ...
Optimal functional-unit assignment and buffer placement for probabilistic pipelines
Applications, such as streaming applications, modeled by task graphs can be efficiently executed in a pipelined fashion. In synthesizing application-specific heterogeneous pipelined systems, where to place buffers (called buffer placement) and what type ...
An overview of micron's automata processor
- Ke Wang,
- Kevin Angstadt,
- Chunkun Bo,
- Nathan Brunelle,
- Elaheh Sadredini,
- Tommy Tracy,
- Jack Wadden,
- Mircea Stan,
- Kevin Skadron
Micron's new Automata Processor (AP) architecture exploits the very high and natural level of parallelism found in DRAM technologies to achieve native-hardware implementation of non-deterministic finite automata (NFAs). The use of DRAM technology to ...
Enabling the high level synthesis of data analytics accelerators
Conventional High Level Synthesis (HLS) tools mainly target compute intensive kernels typical of digital signal processing applications. We are developing techniques and architectural templates to enable HLS of data analytics applications. These ...
Big data analytics on heterogeneous accelerator architectures
In this paper, we present the implementation of big data analytics applications in a heterogeneous CPU+FPGA accelerator architecture. We develop the MapReduce implementation of K-means, K nearest neighbor, support vector machine and Naive Bayes in a ...
Going deeper than deep learning for massive data analytics under physical constraints
Deep Neural Networks (DNNs) are a set of powerful yet computationally complex learning mechanisms that are projected to dominate various artificial intelligence and massive data analytic domains. Physical viability, such as timing, memory, or energy ...
Fault injection at host-compiled level with static fault set reduction for SoC firmware robustness testing
Decreasing hardware reliability makes robust firmware imperative for safety-critical applications. Hence, ensuring correct handling of errors in peripherals is a key objective during firmware design. To adequately support robustness considerations of ...
Optimizing the location of ECC protection in network-on-chip
The communication in Network-on-Chips (NoCs) may be subject to errors. Error Correcting Codes (ECCs) can be used to tolerate the transient faults in flits caused by Single Event Upsets (SEU). ECC can improve the reliability of a NoC significantly at the ...
A disturbance-aware sub-block design to improve reliability of 3D MLC flash memory
The reliability problem of modern flash-memory chips quickly deteriorates because of the nature of MLC chips. Although the vertical stacking of storage cells in 3D flash-memory chips dramatically increases the bit density, compared to 2D chips, it also ...
Self-aware systems for the internet-of-things
The IoT will host a large number of co-existing cyber-physical applications. Continuous change, application interference, environment dynamics and uncertainty lead to complex effects which must be controlled to give performance and application ...
Checkpoint aware hybrid cache architecture for NV processor in energy harvesting powered systems
Energy harvesting is one of the most promising battery alternatives to power future generation embedded systems in Internet of Things (IoT). However, energy harvesting powered embedded systems suffer from frequent execution interruption due to unstable ...
Nano-engineered architectures for ultra-low power wireless body sensor nodes
- Rubén Braojos,
- David Atienza,
- Mohamed M. Sabry Aly,
- Tony F. Wu,
- H.-S. Philip Wong,
- Subhasish Mitra,
- Giovanni Ansaloni
Wireless body sensor nodes (WBSNs) are miniaturized devices that are able to acquire, process and transmit bio-signals (such as electrocardiograms, respiration or human-body kinetics). WBSNs face major design challenges due to extremely limited power ...
Mitigation of homodyne crosstalk noise in silicon photonic NoC architectures with tunable decoupling
Photonic network-on-chip (PNoC) architectures employ photonic waveguides with dense-wavelength-division-multiplexing (DWDM) for signal traversal and microring resonators (MRs) for signal modulation, to enable high bandwidth on-chip transfers. ...
Making the internet-of-things a reality: from smart models, sensing and actuation to energy-efficient architectures
Advances in the physical sciences and engineering enable the development of internet-of-things (IoT) to understand, interface / interact and engineer physical world (systems). However, the deployment of multitude of wireless sensors and agents spanning ...
Web browser workload characterization for power management on HMP platforms
The volume of mobile web browsing traffic has significantly increased as well as the complexity of the mobile websites mandating high-performance web page rendering engines to be used on mobile devices. Although there has been a significant improvement ...
SPARTA: runtime task allocation for energy efficient heterogeneous many-cores
To meet the performance and energy efficiency demands of emerging complex and variable workloads, heterogeneous many-core architectures are increasingly being deployed, necessitating operating systems support for adaptive task allocation to efficiently ...
Energy-efficient mapping of real-time applications on heterogeneous MPSoCs using task replication
In this paper, we study the problem of exploiting parallelism in a hard real-time streaming application modeled as a Synchronous Data Flow (SDF) graph and scheduled on a cluster heterogeneous Multi-Processor System-on-Chip (MPSoC) platform such that ...
Industrial IoT lifecycle via digital twins
Currently, the IoT discussion is focused primarily on the operational phase. This includes how a IoT device behaves, operates, communicates, and interacts with other IoT devices during operation. However, IoT devices and systems have other lifecycle ...
Security and privacy challenges in IoT-based machine-to-machine collaborative scenarios
Security is important in IoT as any other computing systems. However, standard solutions are necessary but not sufficient due to the added dimensions of their presence in physical space and the possibility for them to interact. This talk presents a new ...
Index Terms
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
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Acceptance Rates
| Year | Submitted | Accepted | Rate |
|---|---|---|---|
| CODES+ISSS '13 | 111 | 31 | 28% |
| CODES+ISSS '12 | 163 | 48 | 29% |
| CODES+ISSS '08 | 143 | 44 | 31% |
| CODES+ISSS '05 | 200 | 50 | 25% |
| CODES '01 | 83 | 43 | 52% |
| CODES '99 | 98 | 40 | 41% |
| CODES/CASHE '98 | 66 | 24 | 36% |
| Overall | 864 | 280 | 32% |



