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MEMOCODE '13: Proceedings of the Eleventh ACM/IEEE International Conference on Formal Methods and Models for Codesign
2013 Proceeding
Publisher:
  • IEEE Computer Society
  • 1730 Massachusetts Ave., NW Washington, DC
  • United States
Conference:
October 1 - 20, 2013
ISBN:
978-1-4799-0905-6
Published:
01 October 2013
Sponsors:

Bibliometrics
Abstract

No abstract available.

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Article
APECS: An AADL and polychrony based embedded computing system design environment with an elevator control case study
pp 1–10

Architecture Analysis and Design Language (AADL) is a standard that originated in the avionics domain, but is now being used in avionics and other critical distributed real-time embedded system design. AADL provides a formal notation and semantics for ...

Article
FERAL — Framework for simulator coupling on requirements and architecture level
pp 11–22

Simulation technologies are imperative for embedded systems development. They enable the evaluation of decisions already early in development processes. Simulators are focused on a subset of effects that affect the operation of embedded systems. ...

Article
Fast prototyping from assertions: A pragmatic approach
pp 23–32

We propose a modular approach to automatically prototype communication and control designs from declarative temporal specifications. From each property, we produce a component that observes some operands and generates waveforms for the other operands: ...

Article
Keynote talk I: Building a high-assurance unpiloted air vehicle
pp 33–34

Summary form only given. A drone autopilot is a complex software artifact that includes operating systems, networking, and sensor systems. With support from DARPA, Galois is addressing the challenge of building an open-source high-assurance autopilot ...

Article
Back to basics: Homogeneous representations of multi-rate synchronous dataflow graphs
pp 35–46

Exact temporal analyses of multi-rate synchronous dataflow (MRSDF) graphs, such as computing the maximum achievable throughput, or sufficient buffer sizes required to reach a minimum throughput, require a homogeneous representation called a homogeneous ...

Article
Automated extraction of scenario sequences from disciplined dataflow networks
pp 47–56

Analysing deadlock-freedom, boundedness and realtime constraints are crucial steps in the design of embedded streaming applications. Dataflow models of computation are often used to analyse such properties at design-time. To that end, scenario-based ...

Article
Generation of inductive invariants from register transfer level designs of communication fabrics
pp 57–64

Communication fabrics constitute a key component of multicore processors and systems-on-chip. To ensure correctness of communication fabrics, formal methods such as model checking are essential. Due to the large number of buffers and the distributed ...

Article
Ranking structure in communication fabrics
pp 65–74

We present our experience and case studies for proving liveness of communication fabrics. A methodology is developed that reveals ranking structure underlying the state spaces of such fabrics. This enables an efficient proof of liveness using the k-...

Article
Keynote talk II: Designing tomorrow's chips
pp 75–76

Next generation systems in such domains as wearables and Internet of Things will have capabilities for sensing, recognition and intelligence. Such systems integrate multiple hardware components - including sensors, actuators, compute and commumcations ...

Article
Causal analysis of probabilistic counterexamples
pp 77–86

In probabilistic model checking (PMC), counterexample generation has a quantitative aspect. The counterexample is a set of paths in which a path formula holds, and their accumulative probability mass violates the probability bound. In this paper, we ...

Article
Synthesizing distributed scheduling implementation for probabilistic component-based systems
pp 87–96

Developing concurrent systems typically involves a lengthy debugging period, due to the huge number of possible intricate behaviors. Using a high level description formalism at the intermediate level between the specification and the code can vastly ...

Article
Symbolic software model validation
pp 97–108

Modeling is the crucial first step in formal verification. Some models are constructed by humans from source code, while others are extracted automatically by tools. Regardless of how a model is constructed, verification is only as good as the model; ...

Article
Equivalence checking for synchronous elastic circuits
pp 109–118

Synchronous elastic circuits are clock-based latency insensitive circuits. Elastic circuits are typically synthesized from synchronous circuits. After synthesis, additional buffers can be arbitrarily inserted in the data path of an elastic circuit ...

Article
An equivalence checker for hardware-dependent embedded system software
pp 119–128

This paper presents a novel approach to formally prove the equivalence of low-level hardware-dependent programs. Inspired by hardware verification techniques, a software miter is created that compares the behaviors of two programs, taking into account ...

Article
Keynote talk III: Industry pulse: Trends in function verification
pp 129–130

Recent industry studies point to an accelerated rate at which traditional system-level functionality is being integrated into a single System on Chip (SoC). To address this increasing complexity brought on by higher levels of integration, the industry ...

Article
MEMOCODE 2013 hardware/software co-design contest: Stereo matching
pp 131–134

The MEMOCODE 2013 design contest problem is stereo matching. Given a stereo image pair (i.e., a left image and a right image), the challenge is to infer the depth information (i.e., third dimension) for each pixel in the image utilizing belief ...

Article
Fast and adaptive BP-based multi-core implementation for stereo matching
pp 135–138

The stereo matching problem has been under attention of numerous researchers for many years, due to the wide range of applications in computer vision. The MEMOCODE 2013 design contest was aimed to develop a very fast and efficient stereo matching method ...

Article
FPGA acceleration of Markov Random Field TRW-S inference for stereo matching
pp 139–142

In this paper, we present our hardware accelerator for inference computations on Markov Random Fields (MRFs), which wins the “adjusted run time” category of MEMOCODE 2013 design contest. The contest problem is to accelerate the popular Belief ...

Article
A GPU implementation of tiled belief propagation on Markov Random Fields
pp 143–146

In the MEMOCODE Design Contest 2013, we are participating with a parallelized version of tiled belief propagation method for stereo matching. The proposed algorithm is implemented in CUDA programming model to leverage parallel processing capabilities of ...

Article
Compiler-directed memory hierarchy design for low-energy embedded systems
pp 147–156

In real-time data-intensive multimedia processing applications, data transfer and storage significantly influence, if not dominate, all the major cost parameters of the design space - namely power consumption, performance, and chip area. This paper ...

Article
Safe CCSL specifications and marked graphs
pp 157–166

The Clock Constraint Specification Language (CCSL) proposes a rich polychronous time model dedicated to the specification of constraints on logical clocks: i.e., sequences of event occurrences. A priori independent clocks are progressively constrained ...

Article
Translating synchronous guarded actions to interleaved guarded actions
pp 167–176

In general, guarded actions are well suited to describe systems with different models of computations (MoCs). Different MoCs are thereby obtained by different ways to select actions for execution: In particular, in synchronous models, one executes all ...

Article
Modular compilation of guarded atomic actions
pp 177–188

Over the last decade, Bluespec, a hardware description language of guarded atomic actions has been used to describe rapidly modifiable, modular, no-compromise hardware designs and generate circuits from them. While the language itself supports ...

Article
Tutorial I: Syntax-guided synthesis
pp 189–194

These tutorials discusses the following: Syntax-Guided Synthesis; Firmware Validation Challenges and Opportunities; Secure Programs via Game-based Synthesis; and Network Programming in Frenetic.

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Acceptance Rates

Overall Acceptance Rate34of82submissions,41%
YearSubmittedAcceptedRate
MEMOCODE '19341235%
MEMOCODE '17482246%
Overall823441%