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Supercomputing '88: Proceedings of the 1988 ACM/IEEE conference on Supercomputing
1988 Proceeding
Publisher:
  • IEEE Computer Society Press
  • Washington
  • DC
  • United States
Conference:
Supercomputing88: International Conference for High Performance Computing, Networking, Storage and Analysis Orlando Florida USA November 12 - 17, 1988
ISBN:
978-0-8186-0882-7
Published:
01 November 1988
Sponsors:
SIGARCH, IEEE-CS
In-Cooperation:
NSF, NASA, Supercomputer Edu & Resch Ctr

Bibliometrics
Abstract

No abstract available.

Proceeding Downloads

Article
FAUST: an environment for programming parallel scientific applications
pp 3–10

The subject of integrated programming environments for scientific computing has become very popular over the last few years. Environments such as Rn [3] are being constructed to help coordinate the disjoint activities of editing, debugging, and ...

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Parallel algorithm development workbench
pp 11–17

This paper proposes an approach, and a resulting tool, for developing algorithms for parallel processors. The problems in developing efficient algorithms for parallel systems are discussed. The objectives of this approach are to support the evaluation ...

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Growing discord: programming philosophy and hardware design
pp 18–26

Generally, vector compiler technology has been successful in achieving reasonable peak efficiency on “good” code. Moreover, the community's ability to generate “good” vector code has improved dramatically. As we move into the era of parallelism, ...

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The horizon supercomputing system: architecture and software
pp 28–34

Horizon is the name currently being used to refer to a shared-memory Multiple Instruction stream - Multiple Data stream (MIMD) computer architecture under study by independent groups at the Supercomputing Research Center and at Tera Computer Company. ...

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A processor architecture for horizon
pp 35–41

Horizon is a scalable shared-memory Multiple Instruction stream - Multiple Data stream (MIMD) computer architecture independently under study at the Supercomputing Research Center (SRC) and Tera Computer Company. It is composed of a few hundred ...

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Analysis of a 3D toroidal network for a shared memory architecture
pp 42–46

This paper describes a synchronized network model suitable for the Horizon architecture. The model is defined in terms of a topology and routing policy. A three dimensional toroidal topology is investigated for its multiple redundant paths, memory ...

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Performance prediction for the horizon super computer
pp 48–50

The performance of one Horizon processing element can be quantified by user operations per instruction, the instructions per tick, and the basic clock rate. Assuming there is sufficient parallelism within a problem, the performance of one PE can be ...

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Compiling on horizon
pp 51–52

Compiler research to test several hardware features of the Horizon supercomputer design has yielded some preliminary results based solely on code generation and local optimization. Correctly packing operations into the moderately wide instruction word ...

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HORSE: a simulation of the horizon supercomputer
pp 53–54

HORSE is a program that combines the simulation of the HORIZON multiprocessor architecture with an interactive debugging environment. The models for processing elements, interconnection network, and memory modules include enough detail to allow ...

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The fast fourier transform and sparse matrix computations: a study of two applications on teh HORIZON supercomputer
pp 55–58

As part of the HORIZON project currently underway at the Supercomputing Research Center, a set of application programs are being written and their performance is being evaluated. This paper discusses two of these applications: the fast Fourier transform ...

Article
Assessing the benefits of fine-grain parallelism in dataflow programs
pp 60–69

A method for assessing the benefits of fine-grain parallelism in “real” programs is presented. The method is based on parallelism profiles and speedup curves derived by executing dataflow graphs on an interpreter under progressively more realistic ...

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Tokenless static data flow using associative templates
pp 70–79

The static data flow model of computation promises high performance from fine grained parallelism, but conventional token-driven static data flow architectures are inefficient in terms of memory bandwidth and microcycles required per operation. The ...

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Elimination of bottlenecks in dynamic dataflow processors
pp 80–87

A key component of a dynamic dataflow processor, the matching unit, has been identified as a major bottleneck. An alternate implementation for the matching unit is presented. This implementation increases the operating bandwidth of the unit by allowing ...

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I-NET mechanism for issuing multiple instructions
pp 88–95

Conventional instruction issuing methods use hardware control mechanism to issue instructions in multiple-functional-unit systems. They reach physical limitations due to the complexity of issuing logic when they intend to issue multiple instructions per ...

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Vectorizing compilers: a test suite and results
pp 98–105

This report describes a collection of 100 Fortran loops used to test the effectiveness of an automatic vectorizing compiler. We present the results of compiling these loops using commercially available, vectorizing Fortran compilers on a variety of ...

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An evaluation of vector Fortran 200 generated by Cyber 205 and ETA-10 pre-compilation tools
pp 106–113

Vectorizing pre-compilers such as KAP/205 and VAST-2 complement the efficient use of FORTRAN on the CDC Cyber 205. With the advent of the ETA-10 and its EOS/VSOS environment, the performance of these FORTRAN 200 pre-processors has come under closer ...

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Cedar Fortran and other Vector and parallel Fortran dialects
pp 114–121

The introduction of vector processors and multiprocessors punctuate the most dramatic changes in Fortran and its dialects. The emerging generation of supercomputers utilize both vector processing and multiprocessing simultaneously. The challenge is to ...

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Polycyclic Vector scheduling vs. Chaining on 1-Port Vector supercomputers
pp 122

This paper studies the impact of chaining and several instruction scheduling schemes on one-memory-port vector supercomputers, illustrated by the Cray-1 and Cray-2. The lack of instruction chaining in the Cray-2 vector processor requires a different ...

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Interactive scientific visualization and parallel display techniques
pp 132–139

In this paper, we describe a new graphics environment for essentially real-time interactive visualization of computational fluid mechanics. Within this environment, the researcher may interactively examine fluid data on a framebuffer with animated flow ...

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Design and implementation of a supercomputer frame buffer system
pp 140–147
Article
A scientific visualization workbench
pp 148–155

A system for visualization of data from supercomputer simulations has been developed for use by scientists and engineers at Los Alamos National Laboratory. The scientific visualization workbench, as the system is called, is based on an industry standard ...

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Distributed scientific video movie making
pp 156–162

We describe a versatile, low cost, video movie making system for generating and displaying scientific graphics from remote supercomputers. The system makes video movies by single frame animation from the output of time dependent, numerical simulations ...

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Compiling issues for supercomputers
pp 164–173

Accurate and fast methods for computing data dependencies are vital to the efficiency of vectorizing and parallelizing compilers. Program transformations employed by these compilers are effective only if dependencies are computed as accurately as ...

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Compiling techniques for first-order liner recurrences on a Vector computer
pp 174–181

Linear recurrences are the most important class of non-vectorizable problems in typical scientific/engineering calculations. This work discusses high performance methods for solving first-order linear recurrences on a vector computer, investigates ...

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V-Pascal: an automatic vectorizing compiler for Pascal with no language extensions
pp 182–189

Detailed anatomy of automatic vectorizing compiler V-Pascal (Version 1, now operational) is given. With no language extensions, V-Pascal efficiently vectorizes the whole of arbitrarily given multiply nested for loops using the mechanism of vector ...

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Using Linda for supercomputing on a local area network
pp 192–199

A distributed parallel processing system based on the LINDA programming constructs has been implemented on a local area network of computers. This system allows a single application program to utilize many machines on the network simultaneously. Several ...

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Development of job-job step scheduler for NAL numerical simulator
pp 200–206

In this paper we present the concepts and functions of the job-job step scheduler which is the kernel of the software packages developed for the management of the NAL Numerical Simulator (NS). This scheduler is partially responsible for the high ...

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The symbolic hyperplane transformation for recursively defined arrays
pp 207–214

This paper describes a restructuring transformation which can be used to parallelize recurrence relations. The transformation is based on the hyperplane (or wavefront) method, but extends the applicability of the method to irregularly-structured ...

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Mass storage support for supercomputing
pp 217–221

Mass Storage support for supercomputing at Boeing Computer Services is satisfied by a locally developed storage system known as FMS, the File Management System. The product of a joint development project between CDC and Boeing, it runs on a dedicated ...

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Profiles in mass storage: a tale of two systems
pp 222–228

The Los Alamos Common File System (CFS) and the NCAR Mass Storage System (MSS) are file storage and file management systems that serve heterogeneous computing networks of supercomputers, general purpose computers, scientific workstations and personal ...

Contributors

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Acceptance Rates

Overall Acceptance Rate1,516of6,373submissions,24%
YearSubmittedAcceptedRate
SC '173276119%
SC '164428118%
SC '153587922%
SC '143948321%
SC '134499120%
SC '1246110022%
SC '113527421%
SC '102535120%
SC '092615923%
SC '082775921%
SC '072685420%
SC '062395423%
SC '052606224%
SC '042006030%
SC '032076029%
SC '022306729%
SC '012406025%
SC '001796235%
Supercomputing '952416929%
Supercomputing '933007224%
Supercomputing '922207534%
Supercomputing '912158339%
Overall6,3731,51624%