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DAC '81: Proceedings of the 18th Design Automation Conference
1981 Proceeding
Publisher:
  • IEEE Press
Conference:
Nashville Tennessee USA 29 June 1981- 1 July 1981
Published:
29 June 1981
Sponsors:
SIGDA, IEEE-CS\DATC
Next Conference
June 23 - 27, 2024
San Francisco , CA , USA
Bibliometrics
Abstract

No abstract available.

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CAD for military systems, an essential link to LSI, VLSI and VHSIC technology
pp 3–12

Government involvement in the development of computer aided design (CAD) tools for electronic circuits has a long history.

The advent of large scale integrated (LSI) circuits, going into the 1970's, pulsed the development of the “standard cell” and “...

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Recent developments in representation in the science of design
pp 13–21

A recent goal in computer aided design is the representation of a design artifact in a form sufficient to support all analyses and to determine that the design is realizable. Some aspects of a theory of design representations are presented. Benefits of ...

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The Hughes Automated Layout System - automated LSI/VLSI layout based on channel routing
pp 22–28

The Hughes Automated Layout System (HAL) is intended to provide fast, accurate, and efficient layout of LSI/VLSI circuits. The HAL development plan calls for an evolutionary development in three phases, with each phase providing a usable design system. ...

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An algorithm for searching shortest path by propagating wave fronts in four quadrants
pp 29–36

This paper discusses a new algorithm for searching the shortest path in VLSIs by propagating wave fronts in four quadrants. The algorithm has been experimentally programmed in FORTRAN IV on a Hitac M-200H computer.

The main advantages of this algorithm ...

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Computation of power supply nets in VLSI layout
pp 37–42

For a given placement of macrocells with given power consumption a full automatic layout of power supply and ground nets has been developped. The varying width in different segments of these nets is calculated from local current values resulting in ...

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Design automation status in Japan
pp 43–50

This paper surveys the Japanese design automation (DA) status and activities. First, the DA statistics for major Japanese organizations are presented. These statistics show the status of logic, physical and test DA for digital systems and LSIs. Second, ...

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A design automation system for electronic switching systems
pp 51–58

This paper describes the development and operation experience of NTT's design automation (DA) system for analog/digital switching systems.

The DA system is composed of several subsystems, such as logic design, physical design, documentation and ...

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An integrated computer aided design system for gate array masterslices: Part 1. Logic reorganization system LORES-2
pp 59–65

The outline and the application results of a computer aided logic design system which combines automatic translation of TTL SSI/MSI logic into gate array logic, human intervention, auxiliary logic simulation, and automatic documentation are described. ...

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Creating and updating space occupancy and building plans using interactive graphics
pp 66–73

Interactive graphics systems have been used for generating integrated circuit and printed circuit layouts. Now these systems are being used to create building plans as well. This paper discusses the mechanization of “rent plans” (a set of plans which ...

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Plant design management system (PDMS) in action
pp 74
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Interactive shape generation and spatial conflict testing
pp 75–81

A general purpose, research oriented, interactive modeling system is presented. It is based on two different coherent polyhedral shape representations: a planar graph, used for computation and data manipulation, and a relational-database for compact ...

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Symbolic simulation for functional verification with ADLIB and SDL
pp 82–89

The basic verification problem addressed in this paper is to determine the consistency of two digital design descriptions. This is done by symbolically simulating each description and comparing the results. This approach is complicated by the presence ...

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On proving the correctness of optimizing transformations in a digital design automation system
pp 90–97

As part of our research for the Carnegie-Mellon University Design Automation System, we have been investigating methods for proving that the system produces correct designs from correct specifications. This paper presents a mathematical model of the ...

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Deterministic systems design from functional specifications
pp 98–104

The approach presented is intended to help solve design problems above the logical level. It is based on the use of a special class of PETRI nets to model system components and data flows. Instead of describing an already existing design the functions ...

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Hierarchical design verification for large digital systems
pp 105–112

This paper describes a hierarchical design verification system, consisting of a logic verification subsystem, MIXS (1), a timing verification sybsystem, NELTAS(2), and a hierarchical data base. MIXS is a mixed level simulator, which can handle both ...

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A simulator to replace wire rules for high speed computer design
pp 113–117

Signal quality is of great concern on PC boards containing high speed logic. Improper positioning of loads in a network can cause reflection problems. Traditionally engineers have dealt with this by imposing wire rules on the layout process. The use of ...

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A critical path delay check system
pp 118–123

A Critical Path Delay Check System for designing computers is described. It calculates the critical path delay between the start and end points. It can be used in the early stage of design when, for example, the location of the components on a plug-in ...

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Survey of analysis, simulation and modeling for large scale logic circuits
pp 124–129

The purpose of this paper is to introduce recent developments in the time analysis, simulation and modeling of logic circuits. These advances which have taken place in the circuit and systems area augment the recent advances in logic time simulators. ...

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Routing of printed circuit boards
pp 130–136

A SOFTWARE PROGRAM FOR THE ROUTING OF PRINTED CIRCUIT BOARDS IS DISCUSSED IN THIS PAPER. THIS PROGRAM IS PART OF A SYSTEM WHICH INCLUDES READING DATA FROM THE ENGINEER'S SCHEMATIC DIAGRAM, PLACING THE COMPONENTS ON THE BOARD, AND ROUTING THE ...

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On the use of the linear assignment algorithm in module placement
pp 137–144

This paper examines the application of the computationally powerful linear assignment algorithm to the placement problem. A brief description of the algorithm is given, followed by a discussion of its use with various problem constraints, for improving ...

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Automatic component placement in an interactive minicomputer environment
pp 145–152

A minicomputer-based, second-generation automatic component placement facility has been implemented in the NOMAD System. Features include a new connectivity algorithm and an advanced algorithm for non-modular (no-site) placement.

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PAS-LOP: An automatic module location system for PWB
pp 153–159

In this paper, an automatic module location system for Printed Wiring Boards (PWB's) is discussed. This system is named LOP (LOcation Processor) and is a subsystem of PAS (Packaging Automation System) which is a total design system for PWB's.

The most ...

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A totally integrated systems approach to design and manufacturing at McDonnell Douglas Corporation
pp 160–165

During the 1970s, industry in the United States lost $125 billion of potential production and at least 2 million jobs. Between 1948 and 1968 U.S. output per hour worked increased at an annual rate of 3.2%. For the past seven years this has dropped to ...

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Mechanical design automation in IBM Poughkeepsie
pp 166–170

The IBM Poughkeepsie mechanical design system reduces the cost and time to design and release mechanical parts during the product development cycle. The system uses an interactive graphics design program, CADAM*, and integrates complementary ...

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Application of volumetric modeling to mechanical design and analysis
pp 171–178

Volumetric modeling surpasses surface modeling by allowing certain types of engineering analysis to be performed automatically. In this paper, we describe methods by which a designer may interact with a data base of parts. These methods afford ...

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A perspective view of the MODCON system
pp 179–188

In this paper, a system of computer programs for the geometric description of hot forgings is outlined. The system is known as the MODCON system which stands for MODular CONstruction. The MODCON system allows quite complex forging shapes to be produced ...

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A maximal resolution guided-probe testing algorithm
pp 189–195

The existing guided-probe testing procedures employ a simple strategy of following error path(s). This strategy may fail to locate faults (or may produce a wrong diagnostic) in the following situations:

1. Faults affecting lines connected to buses or ...

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LSI product quality and fault coverage
pp 196–203

At present, the relationship between fault coverage of LSI circuit tests and the tested product quality is not satisfactorily understood. Reported work on integrated circuits predicts, for an acceptable field reject rate, a fault coverage that is too ...

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An algorithmic pretest development for fault identification in analog networks
pp 204–212

This paper describes the design and development of an algorithm for fault identification in electrical analog networks. The emphasis is on mathematical formulation of the problem and generation of a viable fault identification criterion.

The method ...

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Hardware description levels and test for complex circuits
pp 213–219

A complex circuit can be described at the structural level (gate or register transfer description), at the functional level (state based description) or at a higher level (algorithmic or behavioral level).

Test methods have been studied at each level ...

Recommendations

Acceptance Rates

Overall Acceptance Rate1,770of5,499submissions,32%
YearSubmittedAcceptedRate
DAC '0765915223%
DAC '0362815224%
DAC '0249114730%
DAC '9945115434%
DAC '9740013935%
DAC '9637714238%
DAC '9426010038%
DAC '9042712529%
DAC '8946515634%
DAC '8840012531%
DAC '8735113839%
DAC '8630012441%
DAC '8429011640%
Overall5,4991,77032%