MEMOCODE

An executable computational logic can provide the desiredbridge between formal system properties and formalmethods to verify them on the one hand, and executablemodels of system designs based on programming languageson the other. However, not all such ...

System-level design methodologies for embeddedHW/SW systems face several challenges: In order tobe susceptible to systematic formal analysis based onstate-space exploration, a modelling notation with a simpleformal semantics is desired. Architecture-...

This paper proposes a methodology for embeddedsystems co-design, based on statechart models. Theprocess starts with grabbing the system functionalitiesthrough use cases. A set of procedures addressing theimplementation of Statechart models is presented. ...

An interface process generation methodology, based onPetri Nets, is described for fast integrating point-topointcommunicating modules. Formal basis of thismethodology ease behavioral property-checking andconsistent execution of the generated interface ...

We present a concurrency model that allows reasoningabout concurrency in executable specifications. The modelmainly focuses on data-flow and streaming applicationsand at task-level concurrency. The aim of the model is toprovide insight in concurrency ...

We present an extension of the development method Fusion/UML that translates the results of analysis and designinto the formal specification language Object-Z. Theextended process establishes a consistency relationship between analysis and design. ...

Today up to 80% of the design costs for integrated circuitsare due to verification. Verification tools guaranteecompleteness if equivalence of two designs or a propertyfor a design are proven. In the other case usually only onecounter-example is ...

Predicate abstraction has been widely used for modelchecking hardware/software systems. However, for controlintensive systems, existing predicate abstraction techniquescan potentially result in a blowup of the size of the abstractmodel. We deal with ...

We present the formal verification of an Intel Xscale processor model.The Xscale is a superpipelined RISC processor with 7-stage integer, 8-stage memory, and variable-latency multiply-and-accumulate execution pipelines.The processor uses scoreboarding ...

The purpose of this paper is the formal verification oftemporal properties of system-level descriptions that includeboth a control part, which corresponds to a finite setof symbolic states, and a data path with numeric variables.Keeping these variables ...

Because there is a need for engineering changes tofix design errors and satisfy design constraints even afterchip fabrication, design flexibility and debuggabilityare extremely important to provide reliable designs andshorten time-to-market. In this ...

This panel will focus on two problems in formal and semiformalverification of co-design models. First one can be categorizedas Hierarchical verification or compositional verification.The second one is Incremental verification. Advances and challengesin ...

In this paper 1, we present a refinement verification fora class of parameterized systems. These systems are composedof an arbitrary number of similar processes. As in [4]we represent the states by regular languages and the transitionsby transducers ...

Keeping up with the increase in system design complexityrequires the deployment of extensive engineeringre-use technologies [15], so-called platform-based designtechniques [8]. When creating derivatives of such a complexsystems-on-chip (SOC) platform, ...

This paper presents a seamless flow of transformationswhich performs dedicated distributed executive generationfrom a high level specification of a pair: algorithm, architecture. This work is based upon graph models andgraph transformations and is part ...

The use of model checking to validate descriptions ofdigital systems lacks a coverage metrics. The set of provenproperties can be incomplete, thus not guaranteeing the behavioralchecking completeness of the digital system implementationwith respect to ...

cIn this paper, we present a technique for determining tightbounds on the execution time of assembler programs. Thus,our method is independent of the design flow, but takes intoaccount the target architecture to obtain accurate estimates.The key idea is ...

Formal techniques have been widely applied in the designof real-time systems and have significantly helped detectdesign errors by checking real-time properties of themodel. However, a model is only an approximation of itsrealization in terms of the ...

The functioning of the computer as a controlcomponent within a larger overall application, as in theembedded systems, may affect the application'sintegrity as well as people and equipment involved bythe application. A computer like any physical system ...

Today, in general, software is embedded, distributed ontonetworks and structured into logical components thatinteract asynchronously. We study fundamental models ofcomposed software systems and their properties, identifyand describe various basic views, ...

System architects working on SoC design havetraditionally been hampered by the lack of a coherentemethodology for architecture evaluation and coverificationof hardware and software. SystemC 2.0facilitates the development of Transaction-Level Models(TLMs)...

In the design process of SoC (System on Chip), validationis one of the most critical and costly activity. The mainproblem for industrial companies like STMicroelectronics,stands in validation at the complete system level. At thislevel, the properties to ...

We present a generalisation of the supervisory control problemproposed by Ramadge and Wonham. The objective ofthat problem is to synthesise a controller which constrainsa system's behaviour according to a given specification,ensuring controllability and ...

Several efficient compilation techniques have been recentlyproposed for the generation of sequential (C) codefrom Esterel programs. Consisting essentially in direct simulationof the reactive features of the language, these techniquesneed now to be ...

CSP (Communicating Sequential Processes) is a usefulalgebraic notation for creating a hierarchical behaviouralspecification for concurrent systems, due to its formalinterprocess synchronization and communication semantics.CSP specifications are amenable ...

Bluespec has an execution model based on atomic actions.This model is quite different from traditional hardwaredescription languages like Verilog, VHDL and SystemC.Its also different from software languages like C andJava. Bluespec is based on research ...