MOEA/D vs. NSGA-II: A Comprehensive Comparison for Multi/Many Objective Analog/RF Circuit Optimization through a Generic Benchmark

Thanks to the enhanced computational capacity of modern computers, even sophisticated analog/radio frequency (RF) circuit sizing problems can be solved via electronic design automation (EDA) tools. Recently, several analog/RF circuit optimization algorithms have been successfully applied to automatize the analog/RF circuit design process. Conventionally, metaheuristic algorithms are widely used in optimization process. Among various nature-inspired algorithms, evolutionary algorithms (EAs) have been more preferred due to their superiorities (robustness, efficiency, accuracy etc.) over the other algorithms. Furthermore, EAs have been diversified and several distinguished analog/RF circuit optimization approaches for single-, multi-, and many-objective problems have been reported in the literature. However, there are conflicting claims on the performance of these algorithms and no objective performance comparison has been revealed yet. In the previous work, only a few case study circuits have been under test to demonstrate the superiority of the utilized algorithm, so a limited comparison has been made for only these specific circuits. The underlying reason is that the literature lacks a generic benchmark for analog/RF circuit sizing problem. To address these issues, we propose a comprehensive comparison of the most popular two evolutionary computation algorithms, namely Non-Sorting Genetic Algorithm-II and Multi-Objective Evolutionary Algorithm based Decomposition, in this article. For that purpose, we introduce two ad hoc testbenches for analog and RF circuits including the common building blocks. The comparison has been made at both multi- and many-objective domains and the performances of algorithms have been quantitatively revealed through the well-known Pareto-optimal front quality metrics.


INTRODUCTION
Reduction in time to market of the electronic products has become an inevitable task for vendors especially in recent years due to the unbalanced supply-demand.To accelerate the process, several design automation tools have been utilized at different levels of integrated circuit (IC) industry from circuit design to post-manufacturing test [1].The first attempts on the design automation appeared at the end of 1980s, where automation of sizing and layout of digital circuits (floor-planning, placement, and routing) have been studied and successfully accomplished over the years [2][3][4].Nowadays, we have powerful tools that automatically generates the layout even from abstract level designs [5][6][7][8].However, analog/radio frequency (RF) circuit automation problem is quite tedious due the highly nonlinear nature of them [9].Moreover, the devices have become more complicated as the device dimensions are aggressively scaled down.Nevertheless, several design automation tools have been developed to address circuit sizing problem at analog/RF domain [10][11][12][13][14]. Metaheuristic algorithms have been widely used in the circuit synthesis process due to their efficiency and reliability.Conventionally, metaheuristic algorithms are classified under two main categories: Evolutionary Computation (EC) and Swarm Intelligence (SI) [15].The underlying mechanisms of the both algorithms are nature inspired, where EC mimics the Darwin's evolutionary theory [16] while SI-based approaches resemble swarm's communication to exploit computational intelligence [17].The term EC has been diversified as genetic algorithms, evolution strategies, evolutionary programming, and genetic programming in the literature [18].The differences between these algorithms are minor, where the main mechanism is based on evolution of a population through several hundreds/thousands of iterations with recombination, mutation, and selection operators.However, SI algorithms are based on inspiring of intelligent communication between a group of insect colonies or animal societies.A taxonomy of metaheuristic algorithms and a qualitative level of usage of the algorithms in IC synthesis are given in Figure 1.
EC and SI have been comprehensively studied and numerous derivatives of both algorithms have been presented in the literature.Non-Sorting Genetic Algorithm-II (NSGA-II) [19], Multi-Objective Evolutionary Algorithm based on Decomposition (MOEA/D) [20], Strength Pareto Genetic Algorithm-2 (SPEA-2) [21], and Differential Evolution [22] are the well-known EC-based algorithms and have been employed to solve IC sizing problem [23][24][25][26].Moreover, Biased Random Key Genetic Algorithm [27] is another promising EC-based approach and has become popular in recent years; however, it has not been used for IC optimization yet.Particle Swarm [28], Ant Colony Optimization [29], and Artificial Bee Colony [30] are the most appeared SI-based approaches in the literature.Also, they have been applied to IC sizing problem many times [31][32][33] with the level of usage as given in Figure 1.In addition to these approaches, Bacterial Foraging and Artificial Immune System are the other popular SI-based algorithms; however, to our best knowledge, they have not been used for IC synthesis.
Considering the prior work reported in the literature, EC-based approaches are more preferred to solve IC sizing problem, since they have been found the superior for numerical examples [34].The superiority of the evolution may be one possible reason, since the evolution is one of the perfect mechanism in the nature.From the IC sizing point of view, the design process is also quite complex, although not as much as evolution.Moreover, challenging tradeoffs between design objectives under hard design constraints complicate the sizing problem especially for highly nonlinear analog/RF circuits.During the implementation of EC algorithms, we take the advantage of the computational capability of modern computers, where the evolution process can be accelerated (evolving generations within minutes); thus, achieving the best population within reasonable duration from randomly generated initial population.One question arises even if we suppose that EC-based approaches are more convenient for IC sizing problem: Which algorithm is the best in 15:3 terms of effectiveness (cost-performance)?Here, the term cost denotes the synthesis time while the performance is the quality of Pareto-optimal front (POF) that reveals the true performance space of a circuit under certain constraints.As can be seen from Figure 1, a bunch of different EC-based approaches have been developed with several derivatives.Most of the work presented in the literature have focused on either improving the effectiveness of the algorithms or adaptation of newly announced algorithms to the IC sizing problem.Even though they compare their work with one or more other algorithms, the comparison is still insufficient and a bit subjective, since they consider only a few case study circuits, where they degenerate the main algorithm to pave the way of achieving the best solution for a given circuit problem (e.g., increase of mutation rate) but not ensuring whether it does also work for other problems [35][36][37].Here, another further question arises: How can we decide which algorithm is the best for analog/RF IC sizing?To this end, EC-based approaches have been raced many times for analytical problems through well-defined benchmarks [35]; however, the performances for IC sizing problems have not been clearly exhibited yet.Besides, the literature lacks a generic benchmark for analog/RF ICs.A comparison of NSGA-II and MOEA/D for analog circuit optimization is presented in Reference [38]; however, the comparison is performed mostly for single-objective cases.Also POFs are provided for multi-objective cases, where the quality of them are only evaluated by considering inverted generational distance (IGD).In Reference [39], a local constrained multi-objective Bayesian optimization approach is presented and the success of the algorithm are examined on three case study circuits.The quality of the solutions are measured by only IGD metric, too.In this study, we have implemented the most popular EC-based algorithms: NSGA-II and MOEA/D at first.To make an objective comparison, we have introduced testbenches for both analog and RF ICs.The testbench circuits have been synthesized using both algorithms for multi-objective optimization under the same conditions.Moreover, we have also performed many-objective optimization for sample circuits to observe the performances at many-objective domain.To make a quantitative comparison, we have measured qualities of the resultant POFs using widespread performance metrics as well as efficiency evaluation.The remainder of the article is follows.In Section 2, NSGA-II and MOEA/D algorithms are briefly explained as a background.In Sections 3 and 4, we introduce the testbenches 15:4 E. Saǧlican and E. Afacan and provide synthesis results for analog and RF circuits at multi-objective domain, respectively.In Section 5, many-objective optimization results are demonstrated on a couple of sample circuit from the analog benchmark.Section 6, all synthesis results are discussed in detail through a comparison table summarizing the performances (POF quality metric scores) and efficiencies of both algorithms.Finally, Section 7 concludes this paper.

BACKGROUND
Even though NSGA-II and MOEA/D are both EC originated, they have been diversified to achieve the final solution set within the most efficient way.Basically, they create a population from scratch, evolve it through generations using evolutionary mechanisms, select the surviving individuals for the next generation, and achieve the optimized (hypothetically the best) solution at the end of the process.To reveal the difference between competitor algorithms, we briefly explain the fundamental properties of NSGA-II and MOEA/D in this section.

Non-Sorting Genetic Algorithm-II
NSGA-II approach is a derivative of conventional GA, where mating for cross-over and selection mechanisms have been modified.The pseudo-code of NSGA-II is given in Algorithm 1.The algorithm starts with the creation of the first population composed of randomly generated individuals.The size of the first generation is N .Then, the population is expanded through introducing offspring as a product of recombination and mutation operations; hence, the population size becomes 2N .The new population is sorted with respect to the non-domination paradigm.The nondominated solution sets, where the best non-dominated solution set is F 1 and the worse is F k , are selected according to the their ranks until the N individuals are obtained.A good spread of solutions in the POF is also desired.To obtain diversity in the population, density estimation metric and crowded-comparison operator are utilized.To estimate the densities of the solutions, the average of the two objectives is calculated on either side of the solution using Manhattan distance.This quantity, called crowding distance, is an estimate of the perimeter of the cuboid formed by using the nearest neighbors as the vertices.Here, the first and the last solutions in the Pareto-optimal set are considered to be infinite, so the crowding-distance is calculated for objectives between the first and the last objectives with Equation (1) [19], The maximum and minimum values of the objective function parameters are represented as f max and f min , where f i refers to the ith individual set of Pareto-optimal solution.The crowdedcomparison operator that the other operation to obtain diversity helps to provide an uniformly distributed POF, or ((i r ank = j r ank ) and (i dist ance > j dist ance )) According to Equation (2) [19], if two solutions do not belong to the same front, then the solution having lower rank is selected.If both solutions have the same rank, then the solution located a lesser in crowded region is selected.This loop repeats until either the convergence or maximum iteration count is achieved.Further details on the implementation of the algorithm can be found in Reference [19].P t +1 = ∅ and i = 1 7: while Calculate the crowding distance of the front 9: end while 12: Do crowding distance sorting 13: Use selection, crossover and mutation to create new population Q t +1 15: t = t + 1 16: end for 17: Return S

Multi-Objective Evolutionary Algorithm Based on Decomposition
MOEA/D algorithm is a genetic algorithm-based approach that uses decomposition operation.The pseudo-code of MOEA/D is given in Algorithm 2. Decomposition is a function that decomposes to whole multi-objective problem into N scalar sub-problems.In MOEA/D, Tchebycheff decomposition approach aiming at obtaining different solutions of the Pareto-optimal set is used.Different solutions are generated with different scattered weights and the weight space is reduced around the neighbourhood of the best solution.For the weight vector λ = (λ 1 , . . ., λ m ) T , the scalar optimization problem is given in Equation ( 3) [20].The reference point is z * i = (z * i , . . ., z * i ) T , where z * i is the best value for the objective f i .Each Pareto-optimal point x * has a weight vector λ and it's optimal solution.The set of the closest weight vectors compose to a neighborhood of weight vector λ i , minimize For the weight vector, where T denotes the number of weight vector, the closest one is determined by Euclidean distance.Then, initial population is randomly generated.For each sub-problem, the best solutions of two neighbors are selected as parents to create offspring.One point cross-over is used to create the offspring, where a standard mutation operator with relatively low probability (0.01) is applied to produce a new solution.The created offspring is repaired with heuristic operators to improve itself.The ideal reference point is then updated when the offspring value is better than the current reference point.The current solutions in any particular sub-problem are replaced with the generated offspring if the offspring is better otherwise the current solutions survive.The optimization ends up when the maximum iteration count is reached.More details can be found in Reference [20].
On the contrary of non-decomposition multi-objective evolutionary algorithms such as NSGA-II and SPEA-2, MOEA/D achieves diversity with decomposition instead of diversity operator.Generate offspring using genetic operators (y generated from x k and x l ) 7: Repair y to produce y 8: for each j to m do: end for 13: for each index j ∈ B(i) do: 14: if д te (y |λ j , z) ≤ g te (x j |λ j ) do: 15: x j = y 16: FV j = F (y ) 17: end if 18: end for 19: All the vectors are removed from population dominated by F (y ) 20: F (y ) is added to population 21: end for 22: Return S Since the multi-objective problem is decomposed into number of scalar optimization problems in MOEA/D, the diversity inherently occurs.Also, the number of neighborhood is quite important in MOEA/D.When the neighborhood size is small, the parents are closed to each other, so the offspring will be close to the parents (local optima problem).In this case, the algorithm cannot explore new areas in the objective space.Contrarily, if the number of neighborhood is too large, then it is possible to select low performing parents, which may result in unsatisfied offspring as well.However, it is worth noting that this case may not be always negative, since it is not guarantee that unsatisfied parents have always unsatisfied offspring, especially for non-linear problems.

THE PROPOSED ANALOG BENCHMARK AND SYNTHESIS RESULTS OF NSGA-II AND MOEA/D FOR MULTI-OBJECTIVE DOMAIN
To compare NSGA-II and MOEA/D, we introduce an analog benchmark consisting of five fundamental analog building blocks: active-loaded differential amplifier, two-stage OTA, folded cascode OTA, voltage comparator, and bandgap reference circuit.The NSGA-II and MOEA/D algorithms were adopted from Reference [40] and restructured as to be suitable for IC synthesis.The main algorithms were implemented on Phyton, where HSPICE is exploited as the performance estimator.All runs were performed on an AMD Ryzen-9 5900X 12-Core Processor with 64 GB RAM.UMC130-nm technology models were used for all case study circuits.

ANLG1: Active-loaded Differential Amplifier
The first member of the analog benchmark is a conventional active-loaded differential amplifier given in Figure 2. The circuit drives 0.5-pF load, and the supply voltage (V dd ) is 1.2 V. Since there is no symmetrical supply in the circuit, the input transistors of the amplifier are externally biased to all transistors work in saturation region.The bias voltage is also described as a design parameter in the optimization.The circuit topology is quite straightforward: M1 and M2 transistors form the input differential pair, M5 and M6 are the loads, and R, M3, and M4 are the parts of biasing current mirror.
The DC gain (A 0 ) and the unity-gain bandwidth (f t ) were determined as the design objectives, while the power consumption, the chip area, and the phase margin (PM) were defined as the design constraints.The DC gain was also constrained as 0 dB intentionally to avoid individuals having negative gain in the first populations.Design parameters, objectives, and constraints for ANLG1 are tabulated in Table 1.During the synthesis process, the bias voltage, transistor dimensions (pairs are equal), and the resistor values (eight in total) were defined as the design parameters.The population size and the maximum number of iteration were both kept as 100.
The obtained POFs from synthesis with MOEA/D and NSGA-II for two-objective optimization are shown in Figure 3, respectively.As can be seen from the resultant POFs, both algorithms were  able to generate well-distributed POFs quite similar coverage.They have also converged to the final solution together after 50 iterations.

ANLG2: Two-stage OTA
The second analog circuit in the benchmark is a two-stage OTA whose schematic is given in Figure 4.The circuit drives a 0.5-pF load.As the circuit supplied by single voltage of 1.2-V source, the differential pair is also biased externally to keep transistors in saturation.
The topology is similar to ANLG1, where M8 and R b generate the bias current and M5 steers the current from M8 to the differential amplifier (M1-M4).M6 is the second stage of the amplifier in common-source configuration biased by M7, which is also the load of the amplifier.As the circuit  consists of two stages, it has two dominant poles and tends to be unstable.The compensation capacitance is used to split the dominant poles to obtain desired phase margin for safe operation.Again, the DC gain and the unity-gain bandwidth were determined as the design objectives, where the phase margin, the DC gain, the power consumption, and the chip area were determined as the design constraints.All design parameters, objectives, and constraints are listed in Table 2.
The synthesis carried out with 400 generations for 150 population.The total number of design parameters is 14, where pair transistors are kept equal.The obtained POFs are given in Figure 5. Considering the POFs, NSGA-II is slightly better than MOEA/D in terms of objective space coverage, since it achieved wider range in DC gain.Also, NSGA-II has converged to the final solution within 180 iterations while the convergence point for MOEA/D is 185.

ANLG3: Folded Cascode Amplifier
The third member of the analog benchmark is a folded cascode OTA given in Figure 6.Similarly to the other circuits, the circuit is supplied by 1.2-V source while driving 0.5-pF capacitive load.The circuit is externally biased to ensure proper operating point of input transistors, where the bias voltage is also optimized during the synthesis.In the circuit, M1 and M2 are the differential pair of the first stage amplifier.The current created by the cascode current mirror is steered by M4 to the input pair and by M9 and M10 to the output stage.As the second stage amplifier has cascoded transistors, two external bias voltages are applied to the gates of M15-M16 and M7-M8 transistor couples to ensure saturation operation.Since the folded cascode topology has single dominant pole, the circuit does not need any compensation.The DC gain and the unity gain bandwidth were determined as objectives while the phase margin, the power consumption, the chip area, and the gain were determined as the constraints similar to the other amplifiers.Design parameters, objectives, and constraints are provided in Table 3.The circuit optimized for 150 population with 400 iterations.The obtained POFs are given in Figure 7 for multi-objective optimization.MOEA/D has converged to the final POF after 225 iterations where the convergence point for NSGA-II is 290.Furthermore, the design space coverage and the front quality are better in MOEA/D.

ANLG4: Voltage Comparator
Voltage comparator is another building block widely used in many analog applications.Therefore, we have included the voltage comparator circuit given in Figure 8 to the benchmark.The circuit is symmetrically supplied by 0.9-V sources, where the bias voltage is kept at 0.1 V.The transistors M2, M3, M5, and M6 introduce active-loaded amplifier that is biased by M4.The cross-coupled transistors boost the differential gain and balance the output resistance.The common-source amplifier  (M8) connected to the inverter circuit that generates the final comparison signal.The power consumption and the delay were considered as both design objectives and constraints.The aim of delay constraint is elimination of infeasible solutions.Design parameters, objectives, and constraints of the comparator circuit are given in Table 4.Even though the comparator is an analog circuit, the performance is somehow digital.Namely, the circuit should response even if very small change in the input; otherwise, it does not work properly.This situation is a bottleneck for the optimization loop.The optimization may stop when there are many unsatisfied solutions in the first iterations.
To avoid this, we have taken some precautions in the testbench of the circuit.Furthermore, we narrowed the input design parameter space to facilitate the optimization process.The circuit was synthesized for 150 individual with 60 generations.All transistors have the same length to achieve higher speed.The obtained POFs for the voltage comparator are shown in Figure 9.
As seen from the synthesis results, NSGA-II converged to the final POF at the end while MOEA/D cannot reach it.We have also perform additional runs with more iteration counts; however, MOEA/D has stacked at local minima, so the POF could not be obtained.

ANLG5: Bandgap Reference
Even though a bandgap reference (BGR) is one of the most critical building blocks in IC design, there are a few work on optimization of BGR.Therefore, we have selected the well-known Banba BGR [41] as the last member of the analog benchmark, whose schematic is given in Figure 10.The  error amplifier enforces voltages at the inputs to be close to each other for proper operation of the BGR.The PTAT current flows throughout Q 1 and Q 2 , whereas CTAT current flows throughout R 1 and R 2 .The transistors M1-M2-M3 form the current mirror.The start-up circuit (MS1-MS2-MS3-MS4) guaranties that the BGR converges to the proper DC operation point.The circuit is supplied with a single source of 1.8 V.The input referred noise and the power consumption were determined as the objectives.However, the power consumption, the temperature coefficient, and the output voltage are the constraints of the circuit.Design parameters, objectives, and constraints of ANLG5 are shown in Table 5, respectively.
The BGR circuit was synthesized for two objectives, where the total number of design parameters are 11.The number of iterations and the population size are 350 and 150, respectively.The obtained POFs for ANLG5 is given in Figure 11, where the synthesis process has been carried out with 350 iterations for 100 individuals in the population.Even though a rough POF was reached  by MOEA/D, it has not converged to the optimal solution while NSGA-II has achieved the final POF after 290 iterations.

THE PROPOSED RF BENCHMARK AND SYNTHESIS RESULTS OF NSGA-II AND MOEA/D FOR MULTI-OBJECTIVE DOMAIN
RF circuit synthesis is more problematic, since they include capacitor and inductor devices, so the simulation of RF circuits is more complicated and particular analyses, such as steady-state and harmonic balance, are needed to measure the specific performance metrics of RF circuits.Using ideal models for passive devices generate optimistic results, since layout-induced parasitics are not considered.In this article, we used the physical-based parasitic models that successfully cover the layout parasitics as proposed in Reference [42], where the layout and the equivalent circuits of the MIM capacitor and the planar inductor are given in Figure 12.Considering the capacitor model, the metal width (W ), the length (L), and the well spacings (D x and D y ) are the design parameters that are used to calculate the model variables.On the other side, a more complicated model (2 − π ) is used for the inductor due to its sophisticated geometry.W , N t , D o , s, and D x,y denote the metal width, the number of turns, the metal spacing, the outer diameter, and the well spacing, respectively.During simulation of RF circuits, corresponding equivalent circuits of the passive devices are included as subcircuits to the circuit.The major design parameters are N t , D o , and W for the inductor.To evaluate the RF circuit performance, we have employed HSPICERF® tool.A differential cross-coupled LC CMOS oscillator and a MOS cascode LNA circuit were selected as benchmark circuits.

RF1: CMOS Differential Cross-coupled LC Oscillator
The cross-coupled LC oscillator circuit given in Figure 13 is the first member of our proposed RF benchmark.The LC tank is the resonator part of the circuit while the transistors in cross-coupled   2.39 GHz <f o <2.41 GHz Oscillation Peak Amplitude @3ns and @7ns >1V * Phase Noise and Power Consumption are also design objectives to be minimized.structure generate the required negative impedance for the Barkhausen criterion.As the crosscoupled pair formed with complementary MOS, the power consumption reduced with respect to the NMOS only or PMOS only pairs.The circuit works under symmetrical supplies of 1.2 V. To initialize the oscillation, the initial condition statement was determined at the output node as 0.6 V.During synthesis, the phase noise (PN) and the power consumption were considered as design objectives while the frequency and the oscillation amplitude were determined as the design constraints.Here it should be noted that the margin of the oscillation frequency constraints was kept as narrow as possible to achieve the targeted oscillation frequency.Moreover, the oscillation amplitude are measured several times to avoid underdamped response, where the oscillation stops after a certain time.To measure the phase noise response, Harmonic Balance analysis was performed.All design parameters and the corresponding boundaries of the design (transistors' widths and lengths, bias current, capacitor width and length, inductor width, number of turn, metal spacing, and outer diameter) are listed in Table 6.The oscillation amplitudes are checked between 3-4 and 7-8 ns to eliminate solutions having underdamped response.Moreover, lower and upper limits of phase noise, power consumption, and upper and lower limits of oscillation frequency (aiming to keep the frequency within the desired frequency value) are determined as the design constraints.The design objective and the constraints of the RF1 circuit are listed in Table 7.The population size and maximum generation number were determined as 100 and 400, respectively.Even though the number of design parameters are less than the previous circuits, oscillator circuit is highly problematic to be optimized by automatic synthesis tools due to its highly nonlinear behavior and simulation/evaluation difficulties.Since the tool reads the text files generated by SPICE, a suitable testbench is required for reliable evaluation.Therefore, we have measured the oscillation amplitude and the frequency several times to be ensure a sustained oscillation.The obtained POFs of oscillator circuit with MOEA/D and NSGA-II are is provided in Figure 14.As seen from the results, NSGA-II achieved a proper POF while MOEA/D just found the edge solution for the minimum phase noise.There are also a few solutions having the same trajectory, but they are insufficient to form a proper front.

RF2: Cascode Low-noise Amplifier
The second RF benchmark circuit is a 2.4-GHz cascode LNA circuit, whose schematic is provided in Figure 15.Considering the circuit operation, the resonance frequency is determined via L2 and parasitic capacitance at the drain of M2.M3 is used to current steering that created with M1.The circuit operates under single supply voltage of 2.4 V.
Similarly to the oscillator circuit, the planar inductor model given in Figure 12 was used for all inductors.The design parameters and their upper and lower boundaries are listed in Table 8.
The Noise Figure and the power consumption are the objectives while S parameters are considered as constraints.The power consumption was also constrained to limit the power consumption   of the circuit.During simulations, the input and output impedances are matched to 50 Ω using virtual matching networks at simulation environment.The list of design constraints and objectives are provided in Table 9. Synthesis carried out with 500 generations for 50 population.The obtained POFs are given in Figure 16.As can seen from the results, NSGA-II successfully achieved a well-shaped POF after 190 iterations.However, MOEA/D also reached a POF at the end; it is worth noting that the quality of the front is poor in terms of coverage and continuity.

PERFORMANCE OF MOEA/D AND NSGA-II AT MANY-OBJECTIVE DOMAIN
To demonstrate the performance of the algorithms, a comprehensive analysis was performed at the multi-objective domain and results were provided in the previous sections.However, we may have more than two objectives during the optimization of analog circuits.Therefore, the curse of dimensionality should be investigated to examine the performances of the algorithms at manyobjective design domain.To this end, we have also performed many-objective optimization for ANLG1 and ANLG2 circuits.Considering ANLG1, we have defined the power consumption as the third objective.We have kept the all design parameters and the constraints same with the values given in Table 1.Since the design space has been expanded from two dimensions tothree dimensions, we have set the population size to 1,000 (it was 100 for two-objective) while keeping  the iteration count as 100.We have performed all runs under the same conditions and the obtained Pareto-optimal surfaces are given in Figure 17 and Figure 18 for ANLG1 and ANLG2, respectively.
Considering the many-objective optimization results, NSGA-II is also capable of solving threeobjective problems while the solution points are clustered on the surfaces obtained with MOEA/D algorithm.To explore the MOEA/D convergence point, we have extended the iteration count up to 200; however, MOEA/D could not converge to the final solution neither for ANLG1 nor ANLG2.Based on these results, it can be clearly concluded that NSGA-II outperforms over MOEA/D at the many-objective domain.

RESULTS AND DISCUSSION
In the previous sections, the benchmark circuits were introduced and multi-and many-objective synthesis results were provided.To evaluate the synthesis results within a quantitative way and make an objective comparison of MOEA/D and NSGA-II, the most common five different POF quality metrics, Generational distance (GD), IGD, Spacing (S), Spread (Δ), and Maximum Spread (MS), have been utilized [43][44][45].The GD is used to determine how far the evolved solution (obtained front) from real Pareto-optimal solution.To determine GD, the Euclidean distances are measured between for each point of evolved solution and the true POF, and the sum of the measured results are divided by the number of solution of true POFs.The IGD is inverse of GD.It determines how far the true POF from the evolved solution with respect to the evolved solution.
To determine the homogeneity of the obtained front, S is used, which gives the variation of the distance between solutions in the POF.The minimum distance is calculated for each solution with respect to the other solutions and these results are subtracted from the mean value.The square root of the number obtained by dividing the sum of squares of the obtained values by the solution size −1 gives the S value.Δ is used to determine the extent of spread solutions for the obtained POF.If the extreme points of the evolved solution and the true POF are not close to each other, then the spread value will be increased.The MS is the metric giving information how well is the obtained POF covered by the true POF.GD, IGD, Δ, and S should be small while the MS value should be as large as possible for a qualified POF.To evaluate the POF with these metrics, a proper POF is needed; otherwise, the metric values do not provide any meaningful data.To avoid this case, we have also defined a logical operator called Entia, which takes 1 if a proper POF is obtained and vice versa.In addition to these POF metrics, we have also considered the convergence point (CP) to measure the efficiency of the algorithms.Finally, a figure of merit (FoM) that combines all these measures to make an overall evaluation has been defined and calculated according to Equation (4), To obtain the true POFs, all benchmark circuits have been synthesized with increasing the maximum iteration count 4 times larger of their nominal values.For the many-objective circuits, the scores have been calculated for only NSGA-II, where the true POFs were obtained at multiobjective domains (Gain-BW and Power-BW) again using the iteration count 4 times larger than the nominal value.All of the calculated quality metrics, convergence points, entia functions, and the FoM values are summarized in Table 10.Considering the comparison results, MOEA/D is slightly better than NSGA-II to achieve the true POF for ANLG1 and ANLG3 circuits.MOEA/D presents uniform distribution when it is able to solve the multi-objective problem properly.Especially, MOEA/D is better than NSGA-II for relatively simple circuit optimization tasks, because of it is based on decomposition.If we consider homogeneity of POFs, then NSGA-II outperforms MOEA/D as it ensures the diversity with crowding distance calculation.MOEA/D exhibits better performance than NSGA-II for ANLG1 and ANLG3 in terms of delta metric.Although MOEA/D had not solved multi-objective problem for ANLG4, the ability to search of extreme solution points makes the spread metric good enough.But NSGA-II seems superior MOEA/D in terms of finding extreme solution points.Namely, NSGA-II clearly excels MOEA/D for the comparator circuit.
Considering the RF circuits, even though MOEA/D could not found a uniform solution for RF1 circuit, it seems that MOEA/D performed better in terms of generational distance.This is due to the lack of GD metric that gives a limited information when the solution spread into multiple groups.Also, as MOEA/D was found extreme solutions, the algorithm outperforms the NSGA-II in terms of maximum spread.However, it can be concluded that NSGA-II definitely superior to MOEA/D for RF circuits.One possible reason of that the decomposition operator does not work properly especially for circuits having highly non-linear behavior, where there may be many infeasible solutions in the initial generations.The case for many-objective task is quite obvious, where MOEA/D could not converged to any solutions even after 2 times iterations compared to NSGA-II.Meanwhile, NSGA-II was quite able to solve many-objective problems as well as the multi-objective problems.The FOM scores given in the last row also validate these conclusions.

CONCLUSION
EDA tools have been used for many years to facilitate the design process and reduce the time to market.Even though EDA solutions for digital IC design have been fully addressed and commercialized, the analog/RF counterparts have been still in progress.Evolutionary computation-based algorithms have been widely used for automatic sizing of analog circuit.They have been diversified over the years, and many of them have applied to circuit sizing problem.MOEA/D and NSGA-II are the most two EC-based algorithms that have been used in analog/RF sizing problems for many years.However, the performance comparison of these approaches has not been clearly examined due to lack of a generic benchmark for analog/RF circuits.In this article, we have provided a comprehensive comparison of MOEA/D and NSGA-II algorithms in analog/RF IC sizing.For that purpose, we have introduced ad hoc benchmarks for analog and RF circuits and synthesized all the circuits in the benchmarks with both algorithms.The obtained POFs have been compared with true POFs and an objective comparison has been made using the well-known POF quality metrics reported in the literature.Comparison results have revealed that both algorithms perform head to head for relatively simple sizing problems.However, when the circuit becomes more complicated, MOEA/D could not found a proper POF while NSGA-II still performs pretty good.For the many-objective problems, MOEA/D does not work properly even the iteration count is profoundly increased and could not converged to the solution.However, NSGA-II performs well for many-objective problems as well.

ALGORITHM 2 :
The Pseudo Code of MOEA/D.Input: number of subproblems N , a evenly spread of N weight vectors λ 1 to λ m number of the weight vectors in the neighborhood of each weight vector T , index set of T closest weight vector B(i) Output: survivors S 1: Generate the T closest weight vectors for each weight vector 2: Set initial population randomly.(x 1 to x N ) 3: Initialize reference (ideal) point 4: for i to N do: 5:Parents selected using neighborhood selection (x k and x l ) 6:

ALGORITHM 1 :
The Pseudo Code of NSGA-II Input: parent P t , offspring Q t , number of generation G, non-dominated solution set F i

Table 3 .
Design Parameters, Objectives, and Constraints for ANLG3

Table 4 .
Design Parameters, Objectives, and Constraints for ANLG4

Table 7 .
The Design Objectives and the Constraints of RF1

Table 9 .
The Design Objectives and the Constraints of RF2

Table 10 .
The Comparison Table That Summarizes the Synthesis Results and the Scores of the Competitors Algorithms