Upgraded Design of 4-bit Absolute-Value Detector Adopting Simplified Circuit Scheme

In the whole arithmetic integrated digital circuit design, 4-bit absolute-value detector act as an indispensable part throughout the period. Conventionally, the research usually implements the circuit based on the requirement and logic expressions. However, it is also necessary to evaluate the designed circuit with two obvious standards: delay and power consumption. In that case, a specific assessment includes logic effort calculation and gate sizing approach should be taken into serious account to balance these two factors and figure out the optimal way of the circuit design. This paper provides a normal way to judge the related parameters and design, and figure out a relative efficient way to implement the 4-bit absolute value detector (AVD). With the help of the above description, the energy can be largely reduced within just 1.5 times of shortest delay. In that case, a better combination of the design can be worked out, resulting in a more powerful way to the design, and to the whole integrated circuit system.


INTRODUCTION
4-bit absolute-value detector, as one of the basic implementations of bit arithmetic with logic circuits, can help grab a better understanding about digital integrated circuits [1].In many binary systems like digital electronic computers, it is necessary to compare two binary numbers, and then execute the corresponding operations based on the judgement results.From much broader view, comparators act as a small component that is decisive in our supercomputer operation.Besides, comparators are also indispensable in some of exemplified circuit designs, such as temperature alarm, sensors etc. [2,3].Power and area consumption has become major concern in schematic design of these portable devices before their actual implementation in the layout [4].To speed up the calculating process of the computer, it is useful to design a proper device that requires lower energy consumption, shorter delay and less device cost.Since the minimum energy consumption and the minimum delay cannot be guaranteed at the same time, critical path gate sizing is conducted.
This paper mainly describes the process to design an ideal 4bits absolute comparator that is of high efficiency.Firstly, the paper overviews the concept of 2's complement (absolute value), comparator and multiplexer.This part mainly introduces the basic concept of the design.Since then, the whole design can be divided into "absolute value" and "comparator" implementation.Then, with our digital logic design knowledge, we can have many kinds of probable design to achieve the function that depicted before.The second part mainly describes the process and the principle to design the circuit and complete the basic function verification process with the aid of Multism software [5].As for the parameter calculation and clarification part, we calculated the related parameters that is closely linked to the efficiency of the system.Finally, we balance the delay and energy consumption by conducting the V dd and gate sizing optimization, and figure out the optimal way to the problem.Overall, the design has a close relationship with the trending topic in the electronic field such as the integrated circuit design, circuit package and the calculation of the robustness of design in the complete system etc.

DESIGN PROCESS 2.1 Concepts
2.1.1 2's complement.The definition of 2's complement is derived from the implement of the subtraction calculation of two binary numbers.In binary number system, the addition calculation is easily to achieve, with the fundamental rules that "0+0=0, 0+1=1 and 1+1=0 (with a carry to the next bit).However, as for the subtraction, different from the process in decimal, computer do not have the subtractor inside.In that case, it is of great importance to bring up the concept of complement.For instance, we can take A-B as A plus B's complement to achieve the complete same function.
As for the definitions, if the signed number (include minus in the formula) is 1, the corresponding results can be correctly realized by reversing all the unsigned part (0 to 1, 1 to 0) by bits, and then add 1 to the results.In short, it can be summarized as "reverse the number, add 1".If the number represents positive number, the "complementary number" is just equal to the positive number.Then the results can be compared normally, equally to the threshold value that is positive in value.According to the design, it is essential to get the result by comparing the input of the circuit to the threshold value of the circuit.According to the requirement, the output should be 1 if the input is equal or larger than the threshold value.Inversely speaking, if the preset value is larger than the input, the output shown should be 0.
Based on this requirement, it is necessary to design a 3-bit comparator to record the actual outcome of the stage.In binary system, the function of the comparator also varies from the normal decimal comparison, but with some similarities.Firstly, the comparison can be gazed from the MSB (Most Significant Bit), if the numbers are equal, the comparison propagates to the next bit until it makes a difference.If all the bits are same, the output should be set to 1, which represents high voltage in digital circuit.

Multiplexer.
Since the different conditions between the positive and negative inputs should be considered, it is a must to distinguish the above circumstances by adapting the function of multiplexer.The purpose of multiplexing is to combine and transmit signals over a single shared medium in order to optimize efficiency and decrease the total cost of communication [6].
The function of the multiplexer is to select the channel by the enable input.Take 2 to 1 multiplexer as an example, if the enable side inputs 0, then the output will select the binary number from the channel 0, otherwise if the enable side inputs 1, the output will select the binary data that goes into the channel 1.The basic block diagram of the system can be designed as follows in Figure 1.

Absolute value.
Based on the theoretical analysis that shown above, the project can be roughly divided into two parts: absolute value part and 3-bit comparator part.As for the absolute value implementation, the following three methods can be basically adapted, and relative parameters and delays/ gates that used can be compared and figure out the optimal result [7,8].
MUX based on adder.As for the adder implementation methods, the "plus 1" effect can be realized after reversing the unsigned bits with the help of NOT gate.Basically, we can use three half adders.The inputs of these three adders are listed as follows in Table 1.
The basic function and the structure of the adder are listed above.Then all the Sum bits from the adder should be taken out and act as the input separately of the multiplexer.
Table 1: The constitution of the adder structure in the circuit design The first bit of the input, which is also recognized as the signed bit, should be taken as the select enable of the multiplexer.Its function is just similar to the switch.Once the input is 0, the output of the multiplexer will choose channel 0, and the results would be the input itself.If the signed bit is 1 (which represents negative input), the multiplexer will select the input of channel 1, which is set to be the 2's complement of the input number.The circuit design of option 1 is shown in Figure 2.
MUX Based on Combinational Logic.Apart from the half adder implementation, the circuit can also be designed based on the implicated relationship within the logic that hidden inside.We can also implement the 2's complement input with the help of merely the combinational logic.For instance, as for the least significant bit (LSB), the A0' will "AND" 1 to get the sum1 bit.In other words, the output of S1 is totally dependent on the logic level of A0'.Similarly, the logic output of S2 and S3 can also be conducted as follows: Based on the descripted logic relationship, the circuit can be just implemented and go straight through to the channel 1 of the 3 multiplexers.The design is illustrated in Figure 3.
Combinational Logic.After the above description, another possible option can also be taken into account.Do the pure, conventional combinational logic can act as the similar function as the previous two choices?The answer can be easily detected after the truth table and K-map derivation.The truth table of the designed circuit is basically as follows in Table 2. Based on the truth table that illustrated above, the corresponding logic expression can be derived with the help of K-map.0 = 0 (4) Then, the circuit can be implemented with the implementation of the related logic gates that demonstrated in Figure 4 below.
In that case, after all the circuits are verified with the aid of the Multism software, comparisons of some parameters like logic delay, critical path etc should be considered and the best choice should be selected properly.

3-bit Comparator.
After the input value is given, the comparison between input and the threshold value should be done properly to achieve the complete function of the device.Since the first bit of the input and the threshold value are all converted to positive number, the only task that need to be done is to compare the rest 3 bits.As for this function, we divide the realization into two methods.
LSB to MSB.In this schematic design, the comparator bits go from least significant bit (LSB) to most significant bit (MSB) which is shown in Figure 5.   MSB to LSB.In the meanwhile, a proper way can be also figured out if we do the comparison from highest bit to the lowest bit which is shown in Figure 6.
After all the options being implemented, a proper combinational method to realize the 4-bits absolute comparator can be figured out if we consider the gate delays separately which is shown in Table 3.The Inverter's delay T1, And's delay T2, Or's delay T3.For instance, option b of the comparator can be chosen for having a smaller gate delay, and so as for the absolute value realization.Eventually, based on the information that already have, MUX based on combinational logic circuits and MSB to LSB 3-bit comparator are adapted for the whole system.We can test our design with the help of Multism simulation process that shown in Figure 7.

PARAMETER CALCULATION & COMPARISON
In this section, delay and energy consumption should be taken into account.Related parameters should be carefully calculated as a standard to judge whether the design is good or not.

Parameter Analysis & Discussion
According to Figure 7, a critical path should be properly selected to ensure the following calculation to consider the worst case.Within the worst-case range being permitted and recognized, the parameter analysis can proceed.From the following critical path, the critical path contains 11 stages that can be observed in Figure 8.Then, with the help of previous concepts, the path delay and gate sizing optimization can be done properly.For all of the NAND and NOR gates we used the complementary CMOS design, and we assume a unit-sized inverter is W p equal to 650nm, W n equal to 430nm, and L p equal to L n, and equal to 100nm.Then we have: To calculate the logic effort of the whole critical path, logic effort of some common logic gates is what we should comprehend in Table 4 [9].
First, this paper calculates the total stage efforts of the circuits: Then, the stage effort for each stage can be figured out (N=11): Finally, the total parasitic delay is: Based on the above calculation, we can conduct the sizing optimization method of each stages (input capacitance value) that shown in Table 5.
Till this stage, the basic analysis of the design is completed.

Sizing & Vdd Optimization
Gate sizing has a significant impact on the delay, power dissipation, and area of the final circuit [10].Generally, based on our calculations above we got the minimum delay for our circuit design, but our energy has not been optimized yet.We decided to sacrifice our delay to decrease the total energy consumption, and the most delay we can get is 1.5 times the minimum delay we have right now.Assume the delay is proportional to the V dd as shown in formula, and the maximum supply voltage is 1.Then the scarification above can conclude V ddmin with the help of the following two formulas listed together (Assume V T =0.2V): With all the data and equations that listed above, we can work out that the V ddmin =0.7751V.Then the energy consumption under the above circumstances can also be calculated: Since then, three different conditions can be separately considered: V dd optimization only, sizing only, and sizing and V dd optimization in Table 6.By comparing the delay and power consumption, we can find out the relative optimal way to balance those two key parameters.
From the table that illustrated below, a 78% decrease in total energy can be seen when both V ddmin & Sizing take place, which is exactly what we desired.Other methods can also witness an obvious decrease in energy in exchange of more possible delay.

CONCLUSION
Based on the research that given above, we can obtain an optimal way to achieve both shorter delay and less energy consumption.With the help of K-map analysis, we can quickly simplify the circuit and derive the corresponding logic expression.Based on the Multism software, we can verify the function of the circuit and conclude a basic circuit diagram.Then, we use logic effort and gate sizing & V dd optimization approach to get the minimum power source that required under the 1.5 delay circumstances.Finally, we analyze the condition under different circumstances, including minimum delay, V dd min optimization, sizing optimization and both V dd and sizing optimization.By comparing the data that worked out before, we can get the optimal methods to the designed circuit.
This circuits apply V dd & sizing approach properly to obtain a good circuit with the help of parameter calculation and comparison.The methods contained in the analysis can be recognized as efficient and accurate compared to the previous design.It offers a good standard to judge the similar circuits.
However, there are still long way to go.In the future, some analysis software such as Matlab can be adapted to make the results more accurate compared to calculating by hand.Also, whether there exists more efficient circuit are worth discovering.For instance, we can substitute the multiplexer with the corresponding transmission gate to obtain less logic effort, less stages of the circuit can be expected etc.Overall, there are many factors we need to consider and improve in the near future.

Figure 1 :
Figure 1: Block diagram of the AVD design (Photo/Picture credit: Original)

Table 2 :
Truth table implementation of the 4-bit absolute comparator

Table 3 :
The possible gate delay between two possible options of 3-bit comparator

Table 4 :
Logical effort of common gates

Table 5 :
Input capacitance value for each stage

Table 6 :
Optimization results