A Logical Circuit Optimization in Balancing Delay and Energy Consumption

The fast-developing chip manufacturing technique and scaling of transistors allow us to fit more transistors on a small chip. The scaling down process, however, is facing a challenge. The smaller transistors are, the more influential quantum channeling and silicon atom size limit become. To improve efficiency, the solution of scaling down is no longer an option. Therefore, to further improve the efficiency of a chip without scaling down transistors, this paper presents a combinational circuit and focuses on an optimization approach where energy consumption is reduced in exchange for increasing delay. By adjusting the size of transistors, energy is saved while maintaining delay to an acceptable range. This approach manages to reduce energy consumption by about 56% while increasing delay by 50%. This paper represents one of many possible approaches that researchers had and has been working on and this tradeoff can benefit some circuit designs depending on the circuit's purpose and hope to bring some insights on further optimization.


INTRODUCTION
With the advancement of technology, computers have brought us great convenience.The development of computing technology was a process of fitting more transistors on a chip by scaling transistors down [1].However, as the sizes between transistors and silicon atoms are closing in, it is becoming challenging to further scale down transistors [2].At first, a transition from BJT to MOSFET is favored to adapt the fast-developing chips since MOSFETs have better efficiency when power is low and switching frequency is high [3].However, the chip industry is approaching the new upper limit.As a result, finding an alternate solution to improve the performance of nanoscale-integrated chips becomes a trend nowadays.Currently, different designs of transistors and biochips are being explored to increase performance.This paper presents a 4-bit absolute value comparator optimization: an approach of balancing energy consumption and delay to improve performance.This comparator consists of two 4-bit inputs: A and B, where both inputs are in its 2's complement form if is negative.This logical function block is made possible from two parts: converter and comparator.The purpose of the converter is to generate a 3-bit absolute value for both 4-bit input A and B, whereas the purpose of the comparator is to generate 1 if 3-bit input A is larger than 3-bit input B and 0 if otherwise.After the topology phase, the minimum delay is calculated, and the voltage supply is set to 1V.Then, delay and voltage are adjusted to reduce its energy consumption.In the optimization phase, energy consumption is reduced by a significant amount in exchange for a delay increased to 1.5 minimum delay.This trade-off allows us to further reduce the computer's energy consumption without further scaling down transistors.2's complement form is a way of expressing negative figures using binary bits where the first bit always indicates its sign (positive or negative).To convert a positive bit to its negative counterpart, all bits are negated and then add 1; To convert a negative bit to its positive counterpart, the same conversion is used [4].

CIRCUIT DESIGN
Assuming the input capacitance of all inputs is less than or equal to 2-unit sized inverters; C load =32 unit-sized inverter; Gamma (C parasitic/C gate) = 1; Vt=0.2V.
4-bit input A should generate a 3-bit output A' (A2', A1', A0').Since all numbers are in its 2's complement form if the first bit is 0, no conversion is needed, and if the first bit is 1, negate all bits and add 1.The truth table of this converter is found and shown below in Table 1.
A3 is the most significant bit and A0 is the least significant bit.
Comparators compare the most significant bits first, then compare the second most significant bits and until to the least significant bits.A binary number comparator is almost identical to a decimal number comparator.When comparing two decimal numbers, the most significant digits are compared first, if two digits are equal, the second most significant bits are compared, and so on.

CIRCUIT IMPLEMENTATION
With the truth table of both the converter and comparator found, the circuit can be built and simulated using Quartus.The circuit was originally built using AND and OR gates, and every AND gate and OR gate is converted to NOR and NAND gate using Boolean algebra for easier calculation of logical effort and circuit design [5,6].For easier demonstration, the whole circuit is divided into two parts: The converter and the Comparator.

Converter
The converter is built in Quartus and is shown in Figure 1.
Two converters have the same design and convert 4-bit inputs A and B respectively.Take the top converter as an example.this converter takes 4-bit A (A3, A2, A1, A0) as input and generate 3-bit output (A2_Converted, A1_Converted, A0_Converted).
A3 indicates a number sign, therefore, it acts as a selection bit in this circuit.If A3 is 1, multiplexers output their input A, and if A3 is 0, multiplexers output their input B. If A3 is 0, A is positive and input directly goes to output.If A3 is 1, A is negative and each bit is calculated using a logical expression, and logical expressions of 3 bits of output A are:

Comparator
Comparator is built in Quartus and showed in Figure 2.
The comparator takes 2 3-bit inputs A and B. The most significant bits are compared first through logic 2& 2, and this will output 1 if A2 is 1 and B2 is 0. Since these are the most significant bits, if A2 is larger than B2, A is larger than B. If A2 is equal to B2, seconds bits are compared using the same comparison logic.If A1 is equal to B1, then the third bits are compared.By comparing these bits from the most significant bits to the least significant bits, the comparator function is fulfilled.Note: A3, A2, A1, and A0 are 4-bits inputs of this converter.A3 turns from 0 (digital low) to 1(digital high) at approximately 4096us.A2_Converted, A1_Converted, and A0_Converted are 3-bits output.

Minimum Delay and Energy Consumption Calculation
The critical path is found using the method from and shown in Figure 5 [7].
Reference parameters for calculating logical effort and parasitic delay are shown in Table 3.
Input capacitance and Gamma are 1, and load capacitance is 32.On this critical path: (Formulas are referenced from [8].) After parameters of each stage are calculated, data of each stage is listed below in Table 4.
Energy initial = = 82.22,Delay initial = = 24.44.This Energy consumption is when delay is at minimum delay.

Optimization
Since energy is given by ∝ 2 (16) and = , energy consumption calculation becomes to below formula [9]. Then After logging these formulas and values into Excel, excel built-in solver function can be used to find minimum energy consumption by changing sizes and voltage supply and limiting delay to 1.5 minimum delays [10].Adjusted size, Vdd, energy consumption, and delay are shown in Table 5.
Energy Consumption = = 35.73,Total Delay = = 36.66.This Energy consumption is when delay is at 1.5*minimum delay.Energy Consumption Compared with energy consumption at the minimum delay and initial Vdd, energy consumption is decreased by 56.54% and delay is increased by 50%.

CONCLUSION
The density of transistors on microchips had skyrocketed.With more and more transistors, the power consumption of these chips is becoming much more significant than previous.In this design, circuit parameters are leveraged to reduce energy consumption by 56.54%.In this approach, a circuit is drawn to achieve desired objectives.Without changing this circuit design, a tradeoff between energy consumption and delay is proposed and found.By relaxing the delay from a minimum delay to a 1.5 minimum delay, energy consumption is reduced by a significant amount.This design approach shows how optimization works in a computer at the logical gate level.The traditional method of reducing energy consumption is to make the transistor smaller.The optimization process conducted in this experiment had shown an alternate solution to reduce This approach represents one of the many efforts in improving chip efficiency.The advent of new materials could change the whole chip industry.Furthermore, researchers are investing their effort in biochips.The combination of exploration in different paths will further help to reduce energy consumption while maintaining an acceptable delay.

Figure 5 :
Figure 5: Critical Path in Combined Circuit (Photo/Picture credit: Original)

Table 1 :
Truth table of converter Note: ¯ means NOT gate, & means AND gate, | means OR gate and ⊕ means XOR gate

Table 2 :
Truth table of comparator

Table 4 :
Initial Energy Consumption and Delay

Table 5 :
Adjusted size of each stage and voltage for minimum energy consumption at 1.5 minimum delay