DeltaLCA: Comparative Life-Cycle Assessment for Electronics Design

Reducing the environmental footprint of electronics and computing devices requires new tools that empower designers to make informed decisions about sustainability during the design process itself. This is not possible with current tools for life cycle assessment (LCA) which require substantial domain expertise and time to evaluate the numerous chips and other components that make up a device. We observe first that informed decision-making does not require absolute metrics and can instead be done by comparing designs. Second, we can use domain-specific heuristics to perform these comparisons. We combine these insights to develop DeltaLCA, an open-source interactive design tool that addresses the dual challenges of automating life cycle inventory generation and data availability by performing comparative analyses of electronics designs. Users can upload standard design files from Electronic Design Automation (EDA) software and the tool will guide them through determining which one has greater carbon footprints. DeltaLCA leverages electronics-specific LCA datasets and heuristics and tries to automatically rank the two designs, prompting users to provide additional information only when necessary. We show through case studies DeltaLCA achieves the same result as evaluating full LCAs, and that it accelerates LCA comparisons from eight expert-hours to a single click for devices with ~30 components, and 15 minutes for more complex devices with ~100 components.


INTRODUCTION
For the past 70 years, computing devices and systems have been designed with increasing complexity driven solely by demand for computational power and little foresight to sustainability or disposal.As a result, current estimates of climate warming emissions from the overall information and communication technology (ICT) sector range from 2.1-3.9%[15] of total global emissions and are projected to grow rapidly to 8% over the next decade if left unchecked [4].
Reducing these emissions requires not only switching to carbon-free energy sources, but also addressing the more specific problem of embodied carbon that comes from device manufacturing.Particularly for ubiquitous consumer devices like smartphones and laptops, manufacturing accounts for over 80% of life cycle emissions [5].This presents an opportunity to reduce environmental impact (EI) by optimizing future device designs with embodied carbon in mind.Making sustainable design decisions however requires the ability to iteratively analyze a design and determine its carbon footprint which is not possible with today's tools.The environmental impacts of a device, such as those quoted above, are typically quantified retrospectively through a manual Life Cycle Assessment (LCA) in which a human expert analyzes the impacts of the product's production, usage, and disposal.This is challenging for computing devices which are complex systems composed of numerous parts including a CPU, memory, power management circuitry, and much more.For example, the printed circuitboard (PCB) of a consumer device may have 500+ parts [28].
Moreover, mapping this complex inventory to environmental cost requires data about the semiconductor fabrication processes used to make them which are often proprietary to protect intellectual property.As a result, while there exist tools to support users in computing LCA, performing a rigorous assessment requires significant expertise and could take months for complex designs [9,36], and even experts often lack perfect data.This makes it impractical for designers to compute multiple LCAs for different variations of a design, thereby making it hard to take sustainability into account during the design process itself.
We propose a novel approach to sustainability-focused design for reducing manufacturing carbon foorprint of computing devices at the PCB design stage.Our approach is anchored in two principal ideas: Insight 1: Our first key insight is that this design tools should be centered around empowering designers with informed decision-making.This approach recognizes that conducting conventional LCAs for each design alternative is not only costly but also impractical as search spaces become larger.We observe however that informed decision-making does not require absolute metrics, but can be done instead with relative comparisons between different designs.
Insight 2: Our second key insight is that even if we do not have perfect information, we can leverage domain-specific knowledge of electronics manufacturing to reason about these relative differences between parts or designs.
We combine these insights to develop DeltaLCA, an open source interactive design tool that addresses the dual challenges of automating life cycle inventory generation and data availability by performing comparative analyses for electronics.Using this tool users can input two PCB designs using standard output files from Electronic Design Automation (EDA) tools and the tool will guide the users in determining which one has greater carbon footprint.DeltaLCA leverages electronics-specific LCA datasets and heuristics and tries to automatically rank the two designs, prompting users to provide additional information only when necessary, through a user interface designed to highlight missing data.This approach dramatically simplifies LCA computation by canceling out common components, automatically estimating the carbon footprint of remaining components where possible, and provides a user-friendly interface to input new information or use heuristics to automatically compare the remaining parts.
Designing a tool that can compare the environmental impact of electronics designs requires addressing two fundamental challenges.The first challenge is that typical LCAs require developing a highly detailed life cycle inventory (LCI) of the raw materials used, their extraction impacts, manufacturing process steps, and the energy they consume.This is particularly challenging in the electronics because every device is a complex combination of integrated circuits (ICs) and other components that are themselves the result of complex semiconductor manufacturing pipelines and global distribution networks.Large components distributors like Digikey have millions of unique components in their catalogs and there are no comprehensive databases of their environmental impact.
To address this challenge, we develop an automated pipeline to extract relevant LCI data from the outputs of common PCB design tools like KiCAD.We develop a custom Bill-of-Materials (BOM) generator that goes beyond existing tools focused on generating fabrication files to extract detailed information about part classes, footprint sizes, and specifications relevant to environmental analyses using large online parts databases.We then analyze this data to automatically group classes of devices, such as passive components and classes of ICs.We automatically infer essential information for LCA computations such as die size and process technology and combine these with open source measurement data to automate the estimation of carbon footprint for a large class of parts.
While the solutions above provide significant insights into the composition and environmental footprint of a device, there remain significant gaps in the data.This brings us to the second challenge: data availability is a fundamental problem in LCA.To solve this, we look back to our motivation of empowering designers to make sustainable decisions and observe that a common design goal is to reduce environmental impacts compared to a prior version of the same product [2].In these cases, we care more about the relative improvement of the carbon footprint than about the raw impact numbers themselves.As a result, if two designs have a shared set of components with unknown impacts, computing the delta between the designs cancels out these unknowns.
To address the remaining unique parts that are not canceled out, we can take this idea a step further and reduce relative improvement to a binary decision of whether the impact of Design A is greater than Design B. To do this, we leverage both an estimate of the environmental impact (EI) for some parts, whenever these can be computed, and domain-specific heuristics (DSH) which enable us to perform a comparative LCA between parts without having access to full impact data.The final design comparison can then be abstracted into the problem of matching parts of Design A with those from Design B using this partial comparative information.We formulate this matching problem as an integer program, which can be solved efficiently.In cases where a complete match is unattainable, we offer a user interface that displays the unmatched parts, allowing users to contribute additional rules for a conclusive comparison.

We summarize our contributions below:
• DeltaLCA is the first user-in-the-loop design tool that directly empowers electronics designers to make sustainable design decisions by comparing environmental footprints of two different designs.
• We develop an end-to-end pipeline that directly integrates with common electronics EDA tools to automatically generate a parts inventory and extract the key parameters for LCA computation.• We develop methods to infer proprietary information such as die sizes and device process node and use them to automatically estimate carbon footprint of parts for which information is available.Using these we demonstrate fully automated carbon estimates for two designs with full LCAs and prove our method produces a correct comparison result.
• We create a set of five domain-specific heuristics for comparing parts for which data is unavailable using proxies such as die size and minimum package area to identify which has a higher environmental impact.In case studies we find that our tool can match an average of 88% of parts using as few as three heuristics.
• We develop a matching algorithm that sorts unknown parts into classes and synthesizes the environmental impact estimates and domain-specific heuristics to determine which design is more sustainable.Our algorithm can process inputs with 2500 variables in 0.5 s on a laptop enabling real time comparisons.Our case studies incorporating user input for conclusive comparisons when needed accelerated LCA comparisons to 15 min.

ELECTRONICS LCA PRIMER
Performing a Life Cycle Assessment (LCA) involves systematically evaluating the EIs associated with stages of a product's life, from raw material extraction through materials processing, manufacturing, distribution, use, repair and maintenance, and disposal or recycling.This analysis of the total EIs enables manufacturers and consumers to make more informed decisions.The process begins with defining the scope and goal of the assessment, which includes identifying the product to be assessed and the boundaries of the study as shown in Figure 2A.Common LCA boundaries include "cradle-to-gate" assessments which account for raw material extraction through product manufacturing, and "cradle-to-grave" which also includes transport to the consumer, usage throughout the product's lifetime, and end of life disposal.The next step is performing an inventory analysis, where data is collected on every input (energy, water, and materials) and output (such as emissions and waste) associated with each stage of the product's lifecycle.The impact assessment phase interprets this data to understand the EIs, such as global warming potential, ocean acidification, or resource depletion.Finally, the results are interpreted to provide insights and recommendations for reducing the EI.
Figure 2B compiles information from publicly available product environment reports for a number of recent mobile devices.The results show that for many mobile devices the cradle-to-gate emissions of manufacturing and raw materials comprise 70-80% of their lifetime carbon footprint and dominate emissions.This is because unlike devices like servers and desktops which are both physically larger and require constant power during their use phase, mobile devices must be portable and designed for energy consumption in mind to enable long battery life.For this class of devices in particular, sustainable design is critical for further emission reduction beyond switching to clean energy sources.As a result, in this work we focus primarily on evaluating carbon footprint in the manufacturing or cradle-to-gate phase.
How is an LCA computed?We summarize an example of LCA Methodology published by Amazon Devices Sustainability as a case study of how this process is typically conducted by a domain expert evaluating the cradle to gate segment [2]: A device's bill of materials ("BOM") is first obtained from an internal Product Lifecycle Management ("PLM") system.Parts are then assigned to categories as either a mechanical ("ME") component or process versus an electronic ("EE") component.Yield losses are accounted for at each level of the BOM from a series of manufacturing and assembly processes based on a multi-level BOM structure.Manufacturing energy is computed by measuring the total energy required for a process and dividing by the number of devices produced to determine unit energy cost.The emissions for each part    in the BOM are summed to determine the total emissions for manufacturing,   =  =1    .To calculate the emissions, each part must be mapped by an expert to the most appropriate emissions factor available from databases such as ecoinvent, GaBi, industry sources, or academic literature.These emissions factors are generally industry average estimates unless specific supplier data is available.Data availability, however, is a persistent problem in LCA [8].An emissions factor for the IC is chosen based on information available about die size, technology node, and package type.When data is not available, die size is measured for the top five critical ICs in a device and modeled with a conservative emissions factor.Similarly, PCB production is based on total board area, number of layers, and/or mass.
Components such as ICs, PCBs, capacitors and resistors are then scaled by mass or area.Scaling by mass is performed by multiplying the component mass  by an emissions factor   and dividing by the reference mass    and loss factor  to account for waste in the production process,  , = ×      .A similar scaling is applied when using area.The lack of information about IC production presents a key source of uncertainty in this method.The resulting data must then be thoroughly reviewed by experts from the sustainability science team to evaluate data quality issues.
Why is electronics LCA hard?While large companies are able to produce these environmental reports for individual high-value products, it is a challenging and time-intensive process for multiple reasons.The first major challenge in electronics LCA is the sheer number of manufactured parts within a device.For example, a device may be composed of over 500 different components across multiple PCBs [28].Within a device like a laptop or smartphone, some parts are themselves sub-assemblies such as an SSD which has multiple ICs on it.These components include an array of different ICs, resistors, capacitors, inductors, and more.Computing a thorough LCA therefore requires evaluating the impacts of each of these individual parts.Second, individual components are themselves manufactured parts that are the result of a highly complex and resource-intensive fabrication pipeline.For example, IC fabrication is a complex multi-step process involving photolithography, etching and deposition processes and more.Third, even within classes of parts such as ICs or capacitors, the manufacturing processes may differ significantly.This makes it difficult to use a single generic process model for each.For example, capacitors use a wide variety of different dielectric materials.
Different ICs may use different semiconductor materials optimized for high performance (e.g.GaAs for high frequency RF chips) and certain process technology nodes (often denoted by the minimum feature size, 65 nm, 7 nm, etc.) require fundamentally different technologies with significantly higher environmental costs.
These fundamental challenges make it very difficult to evaluate LCA during the design phase.This is compounded by the fact that there is a significant disconnect between tools created to perform LCAs and EDA tools for electronics designers.Traditional LCA tools such as GaBi do not have interfaces to interact with PCB design software and operate fundamentally differently.For example, although GaBi has a database of electronic parts, because of the complexity and variety of semiconductor fabrication processes, its models are industry averages not specific to a chip and sorted instead by package type.Additionally, PCB design tools such as KiCAD and EAGLE do not have any way to output the information required to compute sustainablity metrics such as a chip's die size.This combination makes it a highly manual process requiring significant domain expertise to map a component to one's best guess or approximation in a database.In addition to requiring domain expertise, software such as GaBi is proprietary with licensing fees exceeding $20,000, making it highly inaccessible to electronics designers who seek to optimize for sustainability.

RELATED WORK
Assessing environmental impacts has been explored in multiple domains.We present a survey of related work on relevant topic areas below.

Life Cycle Inventory
Life cycle assessment (LCA) comprises two phases: Life cycle inventory (LCI) and Environmental impact assessment (EIA).LCI serves as the foundation of LCA [21].It involves the compilation and quantification of inputs, outputs, and the potential EIs for a given product throughout its life cycle [34].Therefore, the generation of LCI involves comprehensive data collection about all inputs (e.g., raw materials and energy) and outputs (e.g., emissions and waste) associated with a product's life cycle, which is often the most costly and time-consuming phase [38].Different approaches for generating LCI have been explored for decades with two main focuses: accuracy and boundary completeness [23].Process-based LCI examines every process involved in the life cycle, often used in the studies of products, such as energy products [18] and electronic products [3,32]; input-output-based LCI connects the economic IO model to LCA, offering a broader perspective [26]; hybrid approach combines elements of these two, offers greater accuracy and boundary completeness at the cost of greater time and complexity.Despite decades of research, however, the generation of LCI remains complex and time-consuming and requires a significant amount of manual work.

Environmental Impact Assessment for ICT
A number of works have attempted to estimate the overall impact of the ICT industry as a whole [4,15].Additionally others have developed tools to model embodied and operational emissions, corresponding to the production and use stages of computing devices.The dominating source of emissions, as discussed by Gupta et al. [19,20], is shifting from operational activities toward hardware production for many devices.
Computing devices typically consist of numerous and varied components, each class of which includes a diverse range of materials and processes involved in the production which complicates LCA computation [13].In response to these challenges, there has been a growing body of work focused on developing modeling tools.Much of this work, however, has been concentrated on larger-scale applications, such as data centers [1,14,37], or IC level designs [19].In this work we seek to complement these works by developing a tool for circuitboard level designs to empower designers in the ubiquitous and mobile computing communities to consider sustainability metrics.

Comparative Life Cycle Assessment
Prior work on sustainable development has explored the idea of performing comparative LCA as a decision-making tool, enabling stakeholders to evaluate and compare the EIs of various alternatives and successors [27,39].Comparative LCA is also crucial for making public comparative claims.Despite its importance, these works have only done this by evaluating two complete LCAs and comparing the resulting outputs.This approach to comparative LCAs presents several challenges.First, the cost and time associated with full LCA studies are often prohibitive, particularly in industries like electronics characterized by rapid product development cycles.Second, the complexity of modern supply chains, especially in sectors like electronics, makes the quantification of all processes a time-consuming and resource-intensive task [2,9,36].Third, the requirement for extensive and often confidential data makes full LCAs daunting.
In response to these challenges, recent work developed various methods to streamline the LCA process, i.e., simplified or screening LCA.For instance, certain analysis, known as cradle-to-gate, gate-to-gate, etc, ignores certain upstream or downstream processes [17].Others focus on a narrower range of evaluated environmental metrics [7], which streamlines the inventory phase by reducing the inventory parameter considered in the selected categories.Other approaches simplify the analysis by using mass as a coarse-grained indicator of raw material used [24,29] to perform quicker assessments.
Furthermore, traditional LCA is susceptible to variability in LCA methodologies and software tools between studies.
Inconsistencies in results can be attributed to differences in: • System boundaries.System boundaries determine which processes and life cycle stages are included in the assessment.Even one stage difference can lead to significant variations in the results.• Database differences.If two studies use different data sources, for example, choosing thermal power and nuclear power electricity within the same region could cause 164x of difference [12].Variations across states and even countries can also cause large differences in the calculated LCA results.• Methodological differences.LCA methods can vary in terms of their assumptions.Differences in factors like allocation methods, emissions factors, and modeling assumptions can lead to variations in results.This further complicates the LCA comparison between different designs.We propose a different approach that enables decision-making through relative comparisons between different stages of designs.Canceling out common components between design iterations dramatically simplifies the number of parts to evaluate, and we can then develop ways to reason about which components have more environmental impact.

Sustainability in HCI and Ubicomp
The field of HCI and UbiComp has recently seen an increased interest in sustainable computing.This trend aligns with the broader societal shift towards environmental consciousness.Previous research has focused on unmaking [10,33], the development of biodegradable [6,11,35] and recyclable materials [40] for substrates, and innovative design tools that facilitate the reuse of electronic components [28].It is worth noting that EcoEDA [28] aims to extend the lifespan of electronic parts, thus mitigating the EI of electronic waste.
Most existing research in sustainable computing has been directed towards the end-of-life stage of electronics and primarily focused on new materials.While novel materials are an important part of a holistic sustainability solutions, the EI of a PCB is also significantly influenced by decisions made during its design stage, including the choice of ICs, size, and the integration level of components.Kaebemick et al. [24] emphasize the importance of incorporating environmental considerations into the early design stages.Our work aims to fill the gap in tools to evaluate EI and empower the computing research community to integrate sustainability metrics into the PCB design stage.

SYSTEM OVERVIEW
This section presents an overview of DeltaLCA, a system to assess the relative EI between two input designs A and B.
The differences between the traditional way of comparing two designs and DeltaLCA are illustrated in Figure 1.Traditional LCA workflow.As described in Section 2, a traditional LCA is performed in two phases, the inventory phase and the assessment phase (green and orange boxes), respectively, in Figure 1.Both phases are entirely performed by LCA experts.In the inventory phase, the expert lists all relevant parts of the design file to establish a Complete Parts List.Then, for each part in that list, the expert needs to fill in EI data from an LCA database, such as ecoinvent [38].
Parts, especially recent electronic parts, are often not readily available in these databases, and the expert often needs to search for the best approximation using their domain knowledge, making it impossible to automate this process.In the assessment phase, the expert imports additional processes and establishes a flow diagram in an LCA software, such as GaBi.Creating a flow diagram requires an understanding of both the LCA-specific software and knowledge about the secondary processes and resources needed to manufacture parts.This entire process is done for both input designs, resulting in two EI results.Finally, once the expert has these numbers, they can compare the two designs.
DeltaLCA workflow.In DeltaLCA, we completely automate the inventory phase.We then replace the two assessment phases with a single comparative LCA phase, which requires minimal user feedback.
For the inventory phase, we make use of both insights from Section 1 to automatically establish a Complete Parts List and a Partial LCI.Focusing on a domain-specific tool, in our case a tool for electronic designs, we can leverage our domain knowledge to build an LCA-targeted parser of design files (Insight 2).For each part, we automatically parse all the information available in public datasets and auxiliary sources.The result of this step is a Partial LCI (see Section 5).
A Partial LCI contains three kinds of parts: (1) Parts which are identical and which are present in both A and B. We can cancel these parts out before the comparison algorithm.
(2) Unique parts for which we have sufficient LCA information to compute their EIs.
(3) Unique parts for which we have only partial information.
Parts from type (1) are removed during pre-processing, whereas parts from type (2) are usually encountered in a traditional LCA.To compare parts with partial information (3), we use expert-designed heuristics, which allow us to determine that part   from A will have greater EI than a part   from B without ever computing the actual EI of either part.Intuitively, these heuristics can be thought of as conservative rules, e.g. a heuristic may state that if two ICs are manufactured with the same processes but one is significantly larger than the other, the larger one will have greater EI.This means that the key algorithmic challenge for reasoning about parts with partial information is to perform a pairwise matching between two sets of parts using these heuristics.Importantly, this matching algorithm must also optimally leverage the information that enables computing full EIs for some of the parts.We tackle this challenge with a comparison algorithm which is explained in Section 6.
User-in-the-loop.The output of the comparison algorithm is two design subsets A  and B  (nodes except for the orange ones in Figure 3) for which we can show that the EI of the former is bigger than the EI of latter.For the remaining parts (orange nodes), i.e.A \ A  and B \ B  , our algorithm either has insufficient information about the parts, or design A is simply not more environmentally impactful than design B. In both cases, the user is presented with the comparison result and the remaining parts.To refine the assessment, they can then provide more information to the system by completing part information that the inventory phase has been unable to retrieve or by providing additional, user-defined rules about the relative impact between parts.Once more information has been provided, either about the parts themselves or about the relationship between parts, the comparison result can be updated.Our interactive feedback loop is illustrated in Figure 3 In summary, DeltaLCA automates the inventory phase and the assessment phase as much as possible by leveraging domain-specific knowledge and by canceling out uncertainties through part comparisons.As opposed to the traditional LCA comparison, with DeltaLCA the user is only needed at the end for the actual comparison and not throughout the entire process.

AUTOMATED LIFE CYCLE INVENTORY
The first step in our DeltaLCA pipeline is generating an LCI from PCB design files.Traditional methods for LCI require time and expertise for two key reasons.First, the component models available in LCA software databases do not have a one-to-one mapping to the parts on a PCB which prevents automation.Second, data for many parts is unavailable.
To achieve the desired level of accuracy and automation, we implemented a four-phase pipeline: 1) parsing the raw design files locally.The goal of this step is to extract basic information about the components and board configuration within the PCB design relevant to LCA. 2) interfacing with external datasources to enrich our resulting part lists with up-to-date attributes of each component.3) inferring core specifications, typically kept confidential by manufacturers, with all available information.These specifications, such as the die area of an IC, are crucial for assessing the EIs of ICs. 4) estimating the carbon footprints of standard components with complete information.We describe each phase in detail below.

Create Parts List
Generating parts list from raw PCB design files and accurately categorizing components, while simultaneously extracting detailed information such as size and series, is challenging.We note that computing LCA requires information beyond a typical BOM which is designed for purchasing parts and fabrication and does not contain information about device size or specifications.Generating an accurate parts list is inherently complex due to several key factors: 1) even when PCB designs are created using the same design software, such as Eagle, the components library can significantly differ between projects, resulting in diverse and often customized component symbols and footprints.This inherent variability makes it challenging to establish a uniform and robust parsing algorithm.2) The physical packaging of electronic components can differ significantly, making it challenging to employ a one-size-fits-all algorithm for component categorization.Moreover, classifying between similar components, such as different passive components (e.g., resistors, capacitors, inductors) versus IC packages, necessitates a high degree of domain-specific knowledge.3) Component information is scattered throughout the design files, requiring sophisticated data extraction pipelines to gather the relevant data.4) Detailed electrical specifications of components, such as power consumption, are often not included in the PCB design files.This lack of comprehensive data necessitates the integration of external databases.We focus on three primary EI sources: ICs, PCB substrates, and other electronic components in our implementation.

Parse
Raw PCB Design File.Our automation pipeline is implemented in Python, starting with the extraction of pertinent information from the raw PCB layout files.The parsing method involves several critical steps.First, we calculate the board's dimensions by identifying and processing the coordinates of the outermost wires in the PCB plane.Then, we assess the number of layers by enumerating the activated route layers between the Top (which contains the copper on the top of the board) and Bottom layer markers, indicative of a multilayer PCB structure.The core functionality of parsing begins with systematically iterating through each element in the PCB design, and the goal is to sort all electronic components into four main categories: passive components (e.g., resistor, capacitor, inductor), active components (e.g., diode, transistor), ICs (e.g., microcontroller), and misc (e.g.connectors).
Drawing on research in electronic components guidelines and standard topologies, we propose the following heuristics for the initial categorization: • Element name prefix.We can effectively categorize SMD resistors, capacitors, and inductors into their respective classes by recognizing the prefixes 'R', 'C', and 'L', respectively.These are followed by numeric size identifiers such as '0402' or '0603', which signify the length and width of the package.We employ a set of regular expressions that scan for characteristic prefixes in the designators of components in the raw PCB layout.
• Footprint topology.The physical layout and pin configuration of components also provide significant clues.Specific topology and pad positions are often unique to certain component types.For instance, discrete surface mount transistors are commonly associated with three pins where the three pads in the PCB layout may form a triangular shape; operational amplifiers (op-amps) are often available in 8-pin DIP or SOP packages and have symmetrical pin layouts; microcontrollers are characterized by a higher pin count, typically having 16 pins or more.
• Component correlation.We analyze the network of connections to further aid in their identification.Microcontrollers, which usually serve as the main processing unit on a PCB, can be differentiated by examining the highest density of connections to their footprints.This allows us to distinguish between various ICs and other components that cannot be classified solely based on their element names.
We also determine the core package size of each IC by analyzing the tDocu or tPlace layer, i.e., the silkscreen.
We calculate the extremities of the wires that define the positioning of components in the PCB layout.We exclude components such as fiducial holes and screw terminals from the parsing process to maintain a focus on electronic components.All parsed information is stored with a set of attributes, includingcomponent name, package type, package area, and a quantity which is incremented for each duplicate component.

Call External API.
For each IC, we then initiate a keyword search via Digikey's Product Information API, with the part name serving as the search query.Integrating real-time API calls to comprehensive online databases of electronic component distributors like Digikey enriches the parts list with additional up-to-date technical attributes, such as operational frequency and number of GPIO, that are not typically included within the layout design files themselves.This also enables cross-validation for the information extracted from the user files to resolve custom component libraries.
In the case of empty returns, we attempt modified fuzzy searches by stripping off the suffix to accommodate different naming conventions and improve the search completion rate.Upon successfully receiving a response, DeltaLCA parses the detailed attributes of the top-matched search result returned.We extract the key attributes of ICs such as supplier device package, memory size, and number of pins from the product's attributes.These attributes will be used to infer the specifications of the die, which will be discussed in the section below.Additionally, a fuzzy string matching algorithm is applied to accurately map and retrieve product attributes that may be represented by various terminologies across different data entries.
In Table 1, we compare our method against a range of existing BOM generation tools.The baselines include the built-in BOM generators within commonly used PCB design software such as EAGLE and KiCAD, as well as popular open-source tools like KiCost [25] which can extract component data from several distributors' web servers and InteractiveHtmlBom [22] which has robust local file parsing capabilities.Our parser is the only one that extracts all of the available part information needed to compute LCA.
Table 1.The comprehensiveness of our method compared to existing BOM generation tools.

Generate Partial Inventory
Having established a robust pipeline for local design file extraction with external API integration, we next focus on inferring die specifications in ICs and then generating a partial inventory.
Integrated Circuits, such as microcontrollers, represent the most substantial portion of the environmental footprint in the device manufacturing stage and are more significant than passive components like resistors and capacitors or the PCB substrate itself [6,40].This predominance stems from the high energy cost for semiconductor fabrication plants and raw material cost during the complicated fabrication processes [19].
The die size and process technology node of IC are two main indicators of the environmental footprint from the manufacturing stage because 1) die size determines the amount of raw material used; 2) process technology node which determines the complexity of fabrication: the lithography equipment, patterning process, and associated energy consumed during fabrication.More advanced (smaller) technology nodes and larger die sizes also typically lead to lower yields, which further increase the fraction of the fabrication energy and resources used per chip.Consequently, inferring the die size and process technology node of ICs within the desired error range is crucial for estimating the environmental footprint of a PCB design.

Infer Die Area.
In practice, calculating the precise die size of an IC often requires access to the original IC's design files from semiconductor packaging suppliers.However, these types of proprietary information are typically not readily disclosed by design houses, posing a significant barrier.
We aim to develop a generalized alternative method for approximating die size with readily available information: the dimension of the IC package and package type.The dimensions of the package and its structural characteristics deterimine the maximum silicon area it can house.For example, QFP packages usually have a traditional lead frame with leads extending from all four sides of the package, requiring space for the metal contacts; QFNs do not have leads protruding from the package, and instead, they have an exposed metal pad on the bottom surface; WLCSPs integrate leads within the chip fabrication process, making these a close approximation of the bare silicon die size.Using the GaBi Electronics Extension dataset, we compile a table of die area coefficients, which represent the percentage of each package type occupied by actual silicon.This enables us to rapidly estimate the die area directly from the package size and type with a sufficient level of accuracy.
Using a dictionary of specific package types and their corresponding die size coefficients, we scale each package size by its coefficent to obtain estimated die area.For packages with only one dimension available, the package is assumed to be square, and the area is calculated accordingly.A fuzzy string matching algorithm is applied to determine the best match for the package type within our coefficient dictionary, accounting for any variations in naming conventions and missing package info in the dictionary.
To evaluate our method, we used the Mean Absolute Percentage Error (MAPE), a normalized error metric, as our primary measure.This choice is relevant because the die sizes differ across different MCU series, resulting in varying scales of ground truth values.As shown in Figure 5a, our method demonstrates MAPE of 50.20%, 76.22%, 7.93%, 69.65%, 42.81%, 69.83% for QFN, QFP, DIP, BGA, SSOP, and SO packages, respectively.These values indicate the relative deviation of our estimated die areas from the actual values.Notably, more complex packages like QFP and BGA exhibit higher indeterminacy due to their complex internal structures.

Infer Process Technology Node.
To infer the process technology node used in an MCU, we establish a correlation between the maximum operational frequency and the active current consumption.As the process node size decreases, which implies smaller transistor dimensions, the gate capacitance is reduced.This reduction is proportional to the transistor's switching time due to the diminishing resistive-capacitive (RC) delay, and lower power consumption by minimizing the power dissipation through the channel [31].Consequently, smaller process nodes enable higher operational frequencies while concurrently decreasing active current.Such dual observations act as a heuristic to infer the process technology node.For instance, an MCU operating at a higher frequency with a relatively lower active current than another MCU with similar functionality indicates the use of a more advanced process node.Figure 5b shows the process technology node for 15 commonly used MCU series with publicly available data in relation to their operational frequency and corresponding active current consumption normalized by frequency.We use this data to construct a lightweight classification model to estimate the process node by fitting the known specifications of an MCU with established trends in semiconductors.This method leverages empirical data from semiconductor technology advancements to provide a non-invasive estimation technique that does not rely on direct semiconductor foundry data.

Estimate Partial Environmental Impact
To facilitate a standardized comparison of the environmental footprint in PCB design, we first estimate the cradle-togate carbon footprints of standard fixed components such as resistors, capacitors, inductors, and substrates, that are commonly present in every PCB, in CO2 equivalent.We aim to streamline the process, particularly for users who are new to LCA.
Despite the variability in the materials used for common passive components (capacitors can be made from multilayer ceramic, tantalum, or electrolytic dielectric layers) prior work has shown their EIs are relatively similar [32].Furthermore, compared to major footprint sources like PCB substrates and ICs, the environmental footprint of these passive components is small.Consequently, assigning a single LCA value per component does not result in significant errors.
In our assessment, we standardize the LCA values for these components based on their package size and the results are shown in Table 2.The baseline values are derived from previous research [32] with a functional unit of 1 kg for each component type (e.g., 1 kg MLCC capacitors equates to 97 kg of CO2-eq).For resistors, the environmental footprint ranges from 0.01 grams of CO2 equivalent per piece for 0201 package to 0.6 grams for 1206.Capacitors follow a similar trend, where the EI increases with package size, starting at 0.036 grams of CO2 equivalent for the 0201 size, and rising to 1.067 grams for 0805.Inductors range from 0.022 grams of CO2 equivalent for 0201 to 1.358 grams for 0805.For the PCB substrate material, we selected FR-4, the most commonly used PCB substrate material, which has a standardized environmental footprint of 0.006125 grams of CO2 equivalent per square millimeter per 1mm-thick layer [27,30,40].
For ICs with complete information including die area and process node, we also estimate their carbon footprints using the aggregate carbon footprints per area from Gupta et al. 's work [19].

Overview
The comparison algorithm takes the partial LCIs from the inventory phase for two designs A and B. Without loss of generality, we assume that we want to show that the environmental impact, e.g.carbon footprint, of A is bigger than B.
In general, our algorithm will be able to show this for two subsets A  and B  .Our primary goal is to design an algorithm where B  is maximized, thereby enhancing the likelihood of demonstrating that B has the lowest environmental impact with minimal or no additional user input (i.e., when B  ≡ B).
As mentioned in Section 4, at this stage, partial LCIs contain parts with complete LCA information for which we can perform direct carbon footprint comparison and parts with only partial information which will be compared using pairwise heuristics.But how do we combine heuristic-based comparisons with carbon footprint based comparisons?One straightforward approach would be to first perform an LCA comparison for parts with complete information, so parts that have carbon footprint information, and then, in a second stage to perform a pairwise comparison based on heuristics.
However, this could easily lead to selection problems.Suppose A has only parts with complete information and B has parts with partial information.The first step would consume all parts of A, even if not all of the per-part carbon footprints are necessary to weigh up against the carbon footprint of B. Then, A would not have any parts left for the pairwise comparison.From this example, we can see that the selection of parts used for the carbon footprint comparison and the pairwise, heuristic-based comparison are interdependent.We formulate this interdependent selection problem as an integer program, as described in Section 6.3.Finally, we discuss our implementation and evaluate the performance in Section 6.4.

Heuristics
We define a heuristic H as a map from a subset of parts of design A and a subset of parts of design B to a decision about which subset has a higher carbon footprint, or if neither of them subsumes the other.The heuristic decision is based on certain part attributes and we only assign heuristics between parts that have the necessary attributes available.Heuristics are based on domain knowledge of the application domain and example heuristics to compare PCB components are listed below.We note that these can be extended and modified by the user based on available information: (1) Package size for the same type of passive components.For passive components, such as capacitors and resistors, those of identical dimensions consume comparable amounts of raw materials, making their environmental impact comparable, irrespective of variations in material composition.
(2) Chips with the same core and architecture.Chips that share a common standard core and architecture (e.g., ARM Cortex-M), are considered equivalent in our analysis if they differ only in packaging type.This is underpinned by two factors: the environmental impact of the package is relatively overshadowed by the silicon part; a shared core impies identical manufacturing processes and material usage, thereby equating their environmental footprints.
(3) Equivalent process.In cases where components are analogous in dimensions and weight, we assume that their transportation-related environmental costs are comparable.Furthermore, for components of the same category, the electricity cost in the assembly process, such as soldering, is consistent.
(4) Chip die size.The impact of chip die sizes is twofold.Larger dies not only suggest increased raw material consumption but also tend to result in lower production yields, both contributing to a larger environmental impact.
(5) Process technology node.More advanced (smaller) process technology node requires more steps and complexity in fabrication.This includes the need for advanced lithography equipment and multiple patterning processes, culminating in elevated energy consumption.
(6) Diode size.Across various diode types, such as photodiodes, LEDs, and Schottky diodes, size is an effective indicator of raw material consumption.Given their similar semiconductor structures, the size of the diode correlates directly with the environmental costs associated with raw materials.
We use the first three heuristics to identify parts in A and B which are "identical", i.e. which parts we assume to amount to the same carbon footprint, given the partial information available to use.These parts are being removed before the comparison algorithm.
Note that we have no means of resolving conflicting heuristics.For example if between a chip   and a chip   ,   has a bigger die size (heuristic 4), but   has a smaller process node (heuristic 5), then we have two conflicting pieces of information.Without further information about how to compare these two chips, we have no means of reasoning about them.We therefore remove all heuristics between parts which have conflicting heuristics before our comparison algorithm.

Comparison Algorithm
In the following, we explain the general integer program formulation for the comparison of two designs.Please refer to Figure 6 for a toy example.3. The three example constraints illustrate the three constraints from our integer program formulation.

Carbon footprints A
Carbon footprint variables A Heuristic variables Constraints.b  should only be put to 1 if it has been taken into account by a pairwise heuristic comparison or by means of its carbon footprint, which we translate via the constraint in Eq.2.
where H b  is the set of all binary heuristic variables for heuristics which show that the part B  has been subsumed by some part of A and c b  is a binary variable which is equal to 1 if B  has been used in the carbon footprint computation.
In the toy example in Figure 6, b 2 has been successfully put to 1 because the heuristic ℎ 22 has been selected and  2 's carbon footprint has not been used.
As mentioned earlier, each part A  of A can only be used in one heuristic.But if an A  has already been used in the carbon footprint computation, it cannot be used for pairwise heuristic comparison.This is enforced by the constraint in Eq.3.
(C2) : where H a  is the set of all binary heuristic variables for heuristics which use part A  and c a  is a binary variable which is equal to 1 if A  has been used in the carbon footprint computation.Intuitively, if c a  is equal to 1 then the right-hand side of the constraint is equal to 0 and no heuristic for A  can be selected.If the carbon footprint of A  has not been used for comparison, then c a  is equal to 0, the right-hand side is equal to 1 and at most one heuristic for A  can be selected.The effect of this constraint can be observed in Figure 6, where h 44 could not have been selected because c  4 has already been set to 1.
Finally, we have to include the carbon footprint comparison.For each part with complete information, we assign a weight   which is its actual carbon footprint.To show that the carbon footprint of A is bigger than the carbon footprint of B, we must ensure that the weighted sum of the parts selected for carbon footprint comparison of the former is bigger than the weighted sum of the latter, which is expressed via the constraint in Eq.4.
(C3) : In the toy example in Fig. 6, the left-hand side of this constraint sums up to 20, which is greater than the right-hand side which selects only   3 = 10.
Summary.The objective of the integer program is to maximize the sum of b  (Eq.1).However, to assign b  to 1, either a corresponding heuristic variable h or its carbon footprint variable c b  have to be assigned to 1 (Eq.1).Whereas a heuristic can only be selected if the counterpart in A has not already been used by another heuristic (Eq.3), the carbon footprint can only be used if we have enough carbon footprint in A to counterbalance the use of B  (Eq.4).And we ensure that resources in A are only used once via Eq.2.
Note that theoretically, a part B  could be shown to be subsumed by A via multiple heuristic comparisons and/or carbon footprint comparison at the same time, i.e. we do not enforce comparison uniqueness as for A  in Eq.3.However, it is not advantageous for the solver to put both kinds of variables for B  to 1, since both would have to be weighed up against by parts in A.

Implementation
Integer Program.We implemented the integer program using the Python API of OR-tools [16] and for common comparisons, the runtime is a fraction of a second.Although integer programming is NP-Complete and combinatorial in nature, in practice, solutions to a problem of a reasonable size can be found efficiently.We evaluated the runtime of our comparison algorithm by making pairwise comparisons among eight PCB boards (the three complex designs from the case study (Section 7.1.2)and five smaller designs).As shown in Figure 7, our comparison algorithm's average runtime for a problem of a size similar to the complex design comparisons (i.e., ∼ 2, 500 variables) is around 0.5 seconds and thus enables our UI to run at interactive speeds.the list to emphasize their selection priority, in contrast to matched components shown in gray.The user can create custom comparison rules by selecting components and specifying their quantities via checkboxes and dropdown menus before the component names, and setting the comparison direction through the comparator option menu.Custom user-defined rules are added to a separate table using the 'Add' button, while the 'Del' button allows for the removal of specific rules.The user can then click the 'Update' button to rerun the comparison algorithm taking into account their custom rules.The comparison process concludes once all components, from the design deemed to have a lower EI, are successfully matched.

EVALUATION
Having demonstrated the technical efficacy of our DeltaLCA automated inventory and comparison algorithm and integrating DeltaLCA with a frontend user interface, we evaluated the performance of our end-to-end system with users in the loop.Our study aimed to answer the following questions: Below, we detail the methodology and findings of our two-pronged evaluation approach, encompassing both quantitative analysis and qualitative user feedback.

Case Study
Our case study focused on two key scenarios: simple electronic devices, e.g., those with fewer than 50 components, to assess the tool's direct EI calculation capabilities, and more complex PCBs with missing component information to evaluate the tool's comparison efficiency and the degree of user intervention required.  of DeltaLCA's results, we compared them with the emissions quantified through a traditional Full LCA using GaBi.
DeltaLCA successfully computed the total global warming emissions in carbon dioxide equivalent (CO2-eq) for each design, and determined that BioMouse possesses a lower EI than the Dell mouse (results are shown in Figure 9).The carbon emissions estimated by DeltaLCA are in accordance with GaBi full LCA: the discrepancies stood only at 17.38% for the BioMouse and -46.73% for the Dell mouse.In the context of LCA research, such variances are considered within acceptable bounds.We investigate the difference and find that this results from different environmental impact coefficients for components such as PCBs and capacitors between our analyses.We note that our coefficients were determined from publicly available research papers while the LCAs from [6] were from the Gabi Electronics extension database.
Prior studies, such as those by Smith et al. [32] & Zhang et al. [39] and Liu et al. [27] & Ozkan et al. [30] have acknowledged that LCA results can exhibit up to a three-fold difference even for same products because LCA is susceptible to inconsistencies in methodologies between two studies as we described in Section 3.3 in Related Work.
The expert user who performed the LCA from Arroyos et al. [6] also noted that modeling the the Dell Mouse with standard commercial processes required 2-3 hours while the Biodegradable mouse required 5 hours due to the complexity of modeling a new process flow for the custom water soluble material.This duration only accounts for the time to create the GaBi model and excludes the time required for new component inventory generation.In stark contrast, DeltaLCA achieves a correct comparison result and accelerates the process to a single click.

Complex Design with Partial Inventory (RQ2).
In the realm of electronics design, the assessment of more complex devices is crucial, as they typically incorporate a diverse range of components, and have incomplete component information occurring in their design.To illustrate the benefit of our comparative assessment tool, we did a case study for comparing the carbon footprint of three Arduino dev boards: (1) Arduino Leonardo R3, (2) Arduino MKR FOX 1200, and (3) Arduino UNO Wifi.We choose these devices forseveral reasons: 1) Complexity: Unlike simpler devices like the mouse above, these development boards are akin to small computers, featuring intricate circuitry and multiple-layer design.2) Relevance in UbiComp: these platforms are widely used for prototyping and educational purposes.
Our study involved a cross-comparison of these three devices.One expert with five years of electronics design experience, but no LCA experience, used our tool to establish a relative EI ranking of the three boards, namely (3) ≥ (1) ≥ (2).For reference, we also collected some basic statistics about the three boards in Table A4.If we only deduce the relative ordering based on the information in this table, it is not obvious what the relative order should be.
In fact, the expert user initially tried to prove (2) ≥ (1) with our UI but in the end could not figure out a way to do so and realized that it should be in the opposite direction.This demonstrates that our tool could also serve as a verifier to help users verify their speculation.
As shown in Figure 10, for complex devices like these, containing around 100 components and 20∼30 ICs, our tool's comparative algorithm can automatically match most components (on average 88% overall, and 94% for the target, design B in this case) without any user intervention.Additionally, our tool does not require LCA specific expertise, empowering electronics designers to perform evaluations directly.Such efficiency demonstrates the substantial time savings DeltaLCA offers designers.In our study on complex designs with partial inventories, we highlight the strengths of our comparison algorithm which can utilize both carbon footprint data from automated LCI when available, and also apply expert-defined heuristics when only partial information exists.Moreover, users have the flexibility to create rules for any components across the designs, not just the unmatched ones.This feature is crucial because the matching derived from the integer program may not always be globally optimal and users might have insights on specific components that aren't automatically extracted from PCB design files and online data sources.

User Evaluation & Survey (RQ3)
To deepen our understanding of the tool's utility and effectiveness in real-world scenarios, we conducted user evaluations to understand how designers percieve sustainable design and our tool.The study is composed of two parts.First, we provided a brief background introduction about EI of electronics and guided the participants through a demonstration of DeltaLCA.Second, participants filled out a survey.Please refer to Table A5 for the complete list of our survey questions.It is noteworthy that this study aims to explore designers' awareness of environmental considerations in production, among others.Additionally, it would be intriguing to explore alternative systems that incorporate comparative assessments at different stages of the design pipeline.Although our current research focuses on comparing two final designs, the concept of early-stage comparisons in the design process is a promising area for future work.Such endeavors would likely require not only heuristic but also probabilistic reasoning.
In summary, this work introduces a novel approach to sustainable design with multiple avenues for further exploration.
We hope that our research will both immediately enable designers in the Ubicomp community to develop more sustainable design practices and encourage further investigation into LCA-focused design tools.

Board
Board Area (mm

A CASE STUDY SUMMARY
We summarized the basic attributes of the three Arduino dev boards and user interaction with our tool for comparing the EIs of these devices in the case study.

Fig. 2 .
Fig. 2. A) LCA stages and boundaries.B) Contribution of each stage to total carbon footprint for commercial devices.C) LCA methodology used by Amazon Devices Sustainability [2].

Fig. 3 .
Fig. 3. Our comparison algorithm uses parts either for pairwise comparisons (grey nodes) via heuristics (edges) or for carbon footprint comparison (green nodes).(1) The initial comparison results are first delivered to the user.(2) Drawing from the user's domain knowledge, the user adds comparison rules using any parts available to solve the unmatched parts (orange nodes).(3) The results can be updated, taking into account the user-defined rules.
: (1) the two designs are automatically compared, and the results are delivered to the user; (2) the user can provide additional information to refine the comparison; (3) the comparison result gets updated, taking into account the new information.

Fig. 4 .
Fig. 4. Our automatic LCI pipeline.We start by parsing the PCB design files from common design software into a parts list, then infer core specifications like die sizes leveraging online resources, and finally generate the partial inventory with partial EIs based on publicly available data.

Fig. 5 .
Fig. 5. (a) Performance by package type of our die size estimation in Mean Absolute Percentage Error (MAPE) (N >= 3).QFN: Quad Flat No-lead; QFP: Quad Flat Package; DIP: Dual In-line Package; BGA: Ball Grid Array; SSOP: Shrink Small Outline Package; SO: Small Outline.(b) Trends of process technology nodes across 15 popular MCU series.Each data point represents an MCU series, labeled with its process node in nm, plotted against its maximum operational frequency (MHz) and active current consumption normalized by frequency (mA/MHz).

Fig. 6 .
Fig. 6.Input to this example problem is the bipartite graph, including the heuristic edges and the carbon footprint weights, see Table3.The three example constraints illustrate the three constraints from our integer program formulation.

Fig. 7 .
Fig. 7. Left: The size of the integer program illustrated by the number of variables and the number of constraints for each of the comparisons in the case study (Section 7.1.2) of comparing Arduino dev boards.Right: average runtime in seconds (on a MacBook Pro with M1 chip and 8GB ram) over the size of the problem (represented by number of variables in the integer program).

Fig. 8 .
Fig. 8. System Screenshot of DeltaLCA user interface.(1) The user uploads design files using the buttons in the sidebar.(2) The user is presented with matched/unmatched components.(3) The user specifies custom comparison rules.(4) The user checks all added rules.(5) Updates the comparison results with user-defined rules taken into account.

•
RQ1: Can DeltaLCA accurately calculate the environmental impact (EI) of simple PCB designs with complete information without extra intervention from users?• RQ2: To what extent can DeltaLCA compare and analyze complex PCB designs with incomplete component information, and what is the role of the user in this process?• RQ3: How do electronics designers perceive the importance of EI in PCB design and what are their attitudes towards incorporating tools like DeltaLCA in their workflow?

7. 1 . 1
Complete Inventory with Full LCA (RQ1).We employed DeltaLCA to analyze the EI of two real-world designs obtained from the authors of[6]: a custom biodegradable mouse and a Dell optical mouse.To benchmark the accuracy

Fig. 9 .
Fig. 9. Comparing global warming emissions in carbon dioxide equivalent between DetlaLCA and traditional full LCA using GaBi for a BioMouse (a) and a Dell optical mouse (b).

Figure A 12
FigureA 12  shows that typically fewer than five user-defined rules (specifically, 4, 2, and 1 for the three comparisons) are needed to complete a comparison, with an average time spent of less than 15 minutes per comparison.This is a significant reduction in time compared to traditional LCAs for simpler designs (mouse examples in the previous section).

Fig. 10 .
Fig.10.The matching coverage of our comparison algorithm without any user-defined rules for the three comparisons proving that design A's EI on the left is greater than design B's EI on the right.Our method can automatically find a valid matching that covers most of the parts in design A and design B.Here the parts refer to the list generated by the automated life-cycle inventory process where we turn components like resistors, capacitors, and inductors into a single component 'NonICs' and the base board itself into a single component 'Board'.

Fig. 11 .
Fig. 11.Left: Distribution of users who have considered the environmental impact when designing PCB.Middle: Distribution of users who are inclined to incorporate DeltaLCA into the future design workflow.Right: Distribution of users who think it is important to plug DeltaLCA into existing EDA software, on a scale of 1 to 5 where 1 represents the least importance and 5 represents the most importance.

Fig. 12 .
Fig. 12. Summary of the user interactions with the UI for comparing the three boards.In the subfigures, the red boxes represent unmatched components, and the gray boxes represent matched components.The blue arrow indicates a user-defined rule between components in design A and design B.Here the user is proving A > B for all the three cases, so they stop when all components in B are matched and zero or more components in A are unmatched (indicated with the blue box in the last step).

Table 2 .
Standardized environmental impacts in gram CO2-eq for common passive electronic components (resistors, capacitors, and inductors).

Table 3 .
Carbon footprint values and variable assignments for the example problem from Figure6.Parts for which we do not have complete LCA information have no available carbon footprint.The binary variables are assigned such that the objective function is maximized.Objective function.The goal of the selection problem is to select parts of A and parts of B such that each part of B is shown to be of lesser carbon footprint than some part of A, either by means of direct carbon footprint comparison or by selecting pairwise heuristics.More specifically, we formulate this selection problem as a binary integer program where we associate to each part B  a binary variable b  ∈ {0, 1}.b  is equal to 1 if it the part B  has been included in the LCA comparison.The objective function is shown in Eq.1.We are maximizing the number of compared parts of B since we want to do a comparison for as many parts as possible of that design. b

Table 4 .
2) #Layers #Components #ICs from Automated LCI Basic attributes of the three Arduino dev boards.