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Authors: Bertacco, Valeria
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1997
Result 1 – 20 of 78
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1 published by ACM
June 2012 DAC '12: Proceedings of the 49th Annual Design Automation Conference
Publisher: ACM
Bibliometrics:
Citation Count: 1
Downloads (6 Weeks): 0,   Downloads (12 Months): 3,   Downloads (Overall): 182

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Two misconceptions have been plaguing the electronic design automation (EDA) industry for decades: i) EDA solutions scale to larger complexities at an insufficient rate to keep pace with improvements in silicon designs; and ii) since EDA applications target silicon chip developments, the growth of EDA as an industry is bounded ...
Keywords: EDA, human computing, satisfiability, social networks
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2 published by ACM
August 2006 SBCCI '06: Proceedings of the 19th annual symposium on Integrated circuits and systems design
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 0,   Downloads (12 Months): 1,   Downloads (Overall): 68

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The verification of modern computing systems has grown to dominate the cost of system design, often with limited success, as designs continue to be released with latent bugs. This trend is accelerated by the advent of highly integrated system-on-a-chip (SoC) designs, which feature multiple complex subcomponents connected by simultaneously active ...
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3 published by ACM
August 2006 SBCCI '06: Proceedings of the 19th annual symposium on Integrated circuits and systems design
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 0,   Downloads (12 Months): 0,   Downloads (Overall): 92

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This tutorial addresses state-of-the-art methods used to verify the correctness of sequential digital systems. The focus is on providing an overview of the main technologies and their applicability to complex designs. We cover the baseline algorithms involved in a range of verification methods, their application for specific aspects of formal ...
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4 published by ACM
July 2009 DAC '09: Proceedings of the 46th Annual Design Automation Conference
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 1,   Downloads (12 Months): 8,   Downloads (Overall): 123

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Recent improvements in design verification strive to automate error detection and greatly enhance engineers' ability to detect functional errors. However, the process of diagnosing the cause of these errors, and subsequently fixing them, remains one of the most difficult tasks of verification. The complexity of design descriptions, paired with the ...
Keywords: design verification, error correction, error diagnosis, validation
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5
January 2010 ASPDAC '10: Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Publisher: IEEE Press
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 0,   Downloads (12 Months): 1,   Downloads (Overall): 74

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Escaped errors in released silicon are growing in number due to the increasing complexity of modern processor designs and shrinking production schedules. Worsening the problem are recent trends towards chip multiprocessors (CMPs) with complex and sometimes non-deterministic memory subsystems prone to subtle, devastating bugs. This deteriorating situation is causing a ...
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6 published by ACM
December 2011 MICRO-44: Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Publisher: ACM
Bibliometrics:
Citation Count: 11
Downloads (6 Weeks): 3,   Downloads (12 Months): 18,   Downloads (Overall): 288

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As silicon technology scales, modern processors and embedded systems are rapidly shifting towards complex chip multi-processor (CMP) and system-on-chip (SoC) designs, comprising several processor cores and IP components communicating via a network-on-chip (NoC). As a side-effect of this trend, ensuring their correctness has become increasingly problematic. In particular, the network-on-chip ...
Keywords: formal verification, functional correctness, runtime verification, NoC, network-on-chip
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7 published by ACM
January 2019 ASPDAC '19: Proceedings of the 24th Asia and South Pacific Design Automation Conference
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 2,   Downloads (12 Months): 55,   Downloads (Overall): 55

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Relying on efficient data analytics platforms is increasingly becoming crucial for both small and large scale datasets. While MapReduce implementations, such as Hadoop and Spark, were originally proposed for petascale processing in scale-out clusters, it has been noted that, today, most data centers processes operate on gigabyte-order or smaller datasets, ...
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8
March 2014 DATE '14: Proceedings of the conference on Design, Automation & Test in Europe
Publisher: European Design and Automation Association
Bibliometrics:
Citation Count: 6
Downloads (6 Weeks): 0,   Downloads (12 Months): 2,   Downloads (Overall): 95

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The expected low reliability of the silicon substrate at upcoming technology nodes presents a key challenge for digital system designers. Networks-on-chip (NoCs) are especially concerning because they are often the only communication infrastructure for the chips in which they are deployed. Recently, routing reconfiguration solutions have been proposed to address ...
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9
April 2009 DATE '09: Proceedings of the Conference on Design, Automation and Test in Europe
Publisher: European Design and Automation Association
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 0,   Downloads (12 Months): 1,   Downloads (Overall): 57

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Ensuring correctness of execution of complex multi-core processor systems deployed in the field remains to this day an extremely challenging task. The major part of this effort is concentrated on design verification, where different pre- and post-silicon techniques are used to guarantee that devices behave exactly as stated in the ...
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10 published by ACM
November 2012 ICCAD '12: Proceedings of the International Conference on Computer-Aided Design
Publisher: ACM
Bibliometrics:
Citation Count: 4
Downloads (6 Weeks): 1,   Downloads (12 Months): 1,   Downloads (Overall): 68

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Networks-on-chip (NoCs) have emerged as a favorable solution to provide higher bandwidth interconnects for large chip multiprocessors (CMPs). In order to enhance the inter-connect's performance, the NoC is often designed to include complex components and advanced features. Along with the increase in complexity and size, ensuring the functional correctness of ...
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11 published by ACM
March 2014 ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers: Volume 13 Issue 3s, March 2014
Publisher: ACM
Bibliometrics:
Citation Count: 4
Downloads (6 Weeks): 6,   Downloads (12 Months): 20,   Downloads (Overall): 149

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The increasing number of units in today's systems-on-chip and multicore processors has led to complex intra-chip communication solutions. Specifically, Networks-on-Chip (NoCs) have emerged as a favorable fabric to provide high bandwidth and low latency in connecting many units in a same chip. To achieve these goals, the NoC often includes ...
Keywords: Networks-on-chip, functional correctness, performance monitoring, post-silicon validation
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12
November 2010 ICCAD '10: Proceedings of the International Conference on Computer-Aided Design
Publisher: IEEE Press
Bibliometrics:
Citation Count: 2
Downloads (6 Weeks): 0,   Downloads (12 Months): 0,   Downloads (Overall): 83

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Extreme technology scaling in silicon devices drastically affects reliability, particularly because of runtime failures induced by transistor wearout. Current online testing mechanisms focus on testing all components in a microprocessor, including hardware that has not been exercised, and thus have high performance penalties. We propose a hybrid hardware/software online testing ...
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13
November 2011 ICCAD '11: Proceedings of the International Conference on Computer-Aided Design
Publisher: IEEE Press
Bibliometrics:
Citation Count: 12
Downloads (6 Weeks): 0,   Downloads (12 Months): 3,   Downloads (Overall): 61

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Post-silicon validation has become a crucial part of modern integrated circuit design to capture and eliminate functional bugs that escape pre-silicon verification. The most critical roadblock in post-silicon validation is the limited observability of internal signals of a design, since this aspect hinders the ability to diagnose detected bugs. A ...
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14 published by ACM
June 2014 DAC '14: Proceedings of the 51st Annual Design Automation Conference
Publisher: ACM
Bibliometrics:
Citation Count: 18
Downloads (6 Weeks): 1,   Downloads (12 Months): 18,   Downloads (Overall): 158

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With the advent of multicore processors and system-on-chip designs, intra-chip communication demands have exacerbated, leading to a growing adoption of scalable networks-on-chip (NoCs) as the interconnect fabric. Today, conventional NoC designs may consume up to 30% of the entire chip's power budget, in large part due to leakage power. In ...
Keywords: network-on-chip, routing-reconfiguration, power-gating
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15 published by ACM
June 2019 DAC '19: Proceedings of the 56th Annual Design Automation Conference 2019
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 32,   Downloads (12 Months): 94,   Downloads (Overall): 94

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Graph-based algorithms have gained significant interest in several application domains. Solutions addressing the computational efficiency of such algorithms have mostly relied on many-core architectures. Cleverly laying out input graphs in storage, by placing adjacent vertices in a same storage unit (memory bank or cache unit), enables fast access during graph ...
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16
November 1997 ICCAD '97: Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 34
Downloads (6 Weeks): 1,   Downloads (12 Months): 8,   Downloads (Overall): 362

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We present an algorithm for extracting a disjunctive decomposition from the BDD representation of a logic function F. The output of the algorithm is a multiple-level netlist exposing the hierarchical decomposition structure of the function. The algorithm has theoretical quadratic complexity in the size of the input BDD. Experimentally, we ...
Keywords: disjunctive decomposition , combinational logic optimization
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17 published by ACM
September 2015 NOCS '15: Proceedings of the 9th International Symposium on Networks-on-Chip
Publisher: ACM
Bibliometrics:
Citation Count: 2
Downloads (6 Weeks): 3,   Downloads (12 Months): 25,   Downloads (Overall): 157

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Silicon devices are becoming less and less reliable as technology moves to smaller feature sizes. As a result, digital systems are increasingly likely to experience permanent failures during their life-time. To overcome this problem, networks-on-chip (NoCs) should be designed to, not only fulfill performance requirements, but also be robust to ...
Keywords: Adaptive Routing, Fault-Tolerance, Network-on-Chip
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18 published by ACM
December 2013 MICRO-46: Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
Publisher: ACM
Bibliometrics:
Citation Count: 9
Downloads (6 Weeks): 0,   Downloads (12 Months): 29,   Downloads (Overall): 313

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As silicon continues to scale, transistor reliability is becoming a major concern. At the same time, increasing transistor counts are causing a rapid shift towards large chip multi-processors (CMP) and system-on-chip (SoC) designs, comprising several cores and IPs communicating via a network-on-chip (NoC). As the sole medium of on-chip communication, ...
Keywords: NoC, reconfiguration, diagnosis, permanent faults
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19 published by ACM
June 2017 ISCA '17: Proceedings of the 44th Annual International Symposium on Computer Architecture
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 2,   Downloads (12 Months): 36,   Downloads (Overall): 313

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This work presents a minimally-intrusive, high-performance, post-silicon validation framework for validating memory consistency in multi-core systems. Our framework generates constrained-random tests that are instrumented with observability-enhancing code for memory consistency verification. For each test, we generate a set of compact signatures reflecting the memory-ordering patterns observed over many executions of ...
Keywords: memory consistency model, post-silicon validation
Also published in:
September 2017  ACM SIGARCH Computer Architecture News - ISCA'17: Volume 45 Issue 2, May 2017
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20 published by ACM
March 2008 DATE '08: Proceedings of the conference on Design, automation and test in Europe
Publisher: ACM
Bibliometrics:
Citation Count: 3
Downloads (6 Weeks): 1,   Downloads (12 Months): 4,   Downloads (Overall): 111

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The challenge of verification of multi-core and multi-processor designs grows dramatically with each new generation of systems produced today. Validation of memory coherence of such systems, which include multiple levels of cache and complex protocols, constitutes a major fraction of this task. Unfortunately, current tools are incapable of addressing these ...
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Result 1 – 20 of 78
Result page: 1 2 3 4



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