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2004
Result 1 – 20 of 29
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1 published by ACM
February 2013 FPGA '13: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Publisher: ACM
Bibliometrics:
Citation Count: 1

Dynamic Partial Reconfiguration (DPR) of Xilinx FPGAs in cases where there is significant logic difference between subsequent configurations is made possible by Xilinx module-based PR flow. Xilinx supports this flow only for high-end FPGAs and requires paid license, without which Xilinx PlanAhead software disables the related knobs and features. This ...
Keywords: dynamic partial reconfiguration
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2 published by ACM
September 2004 SBCCI '04: Proceedings of the 17th symposium on Integrated circuits and system design
Publisher: ACM
Bibliometrics:
Citation Count: 31
Downloads (6 Weeks): 2,   Downloads (12 Months): 12,   Downloads (Overall): 706

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Xilinx Virtex FPGAs offer the possibility of dynamic and partial run-time reconfiguration. If a system uses this feature the designer has to take care, that no signal lines cross the border to other reconfigurable regions. Traditional solutions connecting modules on a dynamic and partial reconfigurable system use TBUF elements for ...
Keywords: dynamic partial reconfiguration, virtex
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3 published by ACM
May 2016 ACM Transactions on Embedded Computing Systems (TECS): Volume 15 Issue 3, July 2016
Publisher: ACM
Bibliometrics:
Citation Count: 1
Downloads (6 Weeks): 5,   Downloads (12 Months): 17,   Downloads (Overall): 109

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Dynamically reconfigurable hardware has been identified as a promising solution for the design of energy-efficient embedded systems. However, its adoption is limited by costly design effort, including verification and validation, which is even more complex than for nondynamically reconfigurable systems. In this article, we propose a tool-supported formal method to ...
Keywords: Dynamical partial reconfiguration, automata models
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4 published by ACM
October 2015 RACS: Proceedings of the 2015 Conference on research in adaptive and convergent systems
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 0,   Downloads (12 Months): 8,   Downloads (Overall): 60

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Partial reconfigurable three-dimensional field programmable gate arrays are promising innovations for meet the demand of implementing embedded systems demonstrating high area efficiency and excellent performance. However, thermal management has become a critical concern in three-dimensional integrated systems; this is because high system temperatures degrade system performance. This study proposes an ...
Keywords: task placement, 3D FPGAs, dynamically partially reconfiguration
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5 published by ACM
August 2013 ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special Section on 19th Reconfigurable Architectures Workshop (RAW 2012): Volume 6 Issue 2, July 2013
Publisher: ACM
Bibliometrics:
Citation Count: 1
Downloads (6 Weeks): 3,   Downloads (12 Months): 11,   Downloads (Overall): 351

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In most existing works, reconfigurable hardware modules are still managed as conventional hardware devices. Further, the software reconfiguration overhead incurred by loading corresponding device drivers into the kernel of an operating system has been overlooked until now. As a result, the enhancement of system performance and the utilization of reconfigurable ...
Keywords: Dynamically partially reconfigurable systems, hardware virtualization
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6 published by ACM
October 2009 ACM Transactions on Embedded Computing Systems (TECS): Volume 9 Issue 1, October 2009
Publisher: ACM
Bibliometrics:
Citation Count: 10
Downloads (6 Weeks): 3,   Downloads (12 Months): 15,   Downloads (Overall): 600

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In this article, we propose field programmable gate array-based scalable architecture for discrete cosine transform (DCT) computation using dynamic partial reconfiguration. Our architecture can achieve quality scalability using dynamic partial reconfiguration. This is important for some critical applications that need continuous hardware servicing. Our scalable architecture has three features. First, ...
Keywords: DCT, FPGA, ME, dynamic partial reconfiguration, scalability
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7 published by ACM
September 2008 SBCCI '08: Proceedings of the 21st annual symposium on Integrated circuits and system design
Publisher: ACM
Bibliometrics:
Citation Count: 3
Downloads (6 Weeks): 1,   Downloads (12 Months): 8,   Downloads (Overall): 299

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This paper presents an innovative method that allows the use of dynamic partial reconfiguration combined with triple modular redundancy (TMR) in SRAM-based FPGAs fault-tolerant designs. The method uses large grain TMR with special voters capable of signalizing the faulty module, and check point states that allow the sequential synchronization of ...
Keywords: FPGA, TMR, dynamic partial reconfiguration, fault tolerance
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8 published by ACM
February 2014 FPGA '14: Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
Publisher: ACM
Bibliometrics:
Citation Count: 0

Reconfiguration technique has been considered as one of the most promising electronic design automation (EDA) technologies in MPSoC design paradigms. However, due to the unavoidable latency in the reconfiguration procedure, it still poses a significant challenge to efficiently analyze the trade-offs for the software/hardware execution, static reconfiguration and dynamic reconfiguration. ...
Keywords: dynamic partial reconfiguration, eda, fpga, heterogeneous mpsoc, trade-offs
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9 published by ACM
June 2017 SCOPES '17: Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 2,   Downloads (12 Months): 37,   Downloads (Overall): 107

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Approximate Computing aims at trading off computational accuracy against improvements regarding performance, resource utilization and power consumption by making use of the capability of many applications to tolerate a certain loss of quality. A key issue is the dependency of the impact of approximation on the input data as well ...
Keywords: SoC, Image Processing, Approximate Computing, Dynamic Partial Reconfiguration, FPGA
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10 published by ACM
December 2012 ACM Transactions on Reconfigurable Technology and Systems (TRETS): Volume 5 Issue 4, December 2012
Publisher: ACM
Bibliometrics:
Citation Count: 3
Downloads (6 Weeks): 0,   Downloads (12 Months): 12,   Downloads (Overall): 522

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Traditionally, hardware circuits are realized according to techniques that follow the classical phases of design and testing. A completely new approach in the creation of hardware circuits has been proposed---the Evolvable Hardware (EHW) paradigm, which bases the circuit synthesis on a goal-oriented evolutionary process inspired by biological evolution in Nature. ...
Keywords: Reconfigurable hardware, dynamic partial reconfiguration, evolutionary circuit design, evolvable hardware
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11 published by ACM
December 2014 ACM Transactions on Reconfigurable Technology and Systems (TRETS): Volume 7 Issue 4, January 2015
Publisher: ACM
Bibliometrics:
Citation Count: 3
Downloads (6 Weeks): 0,   Downloads (12 Months): 7,   Downloads (Overall): 136

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There is strong interest in the development of dynamically reconfigurable systems that can meet real-time constraints on energy, performance, and accuracy. The generation of real-time constraints will significantly expand the applicability of dynamically reconfigurable systems to new domains, such as digital video processing. We develop a dynamically reconfigurable 2D FIR ...
Keywords: 2D separable FIR filtering, Dynamic partial reconfiguration, FPGA
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12 published by ACM
October 2014 WESS '14: Proceedings of the 9th Workshop on Embedded Systems Security
Publisher: ACM
Bibliometrics:
Citation Count: 2
Downloads (6 Weeks): 22,   Downloads (12 Months): 111,   Downloads (Overall): 266

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We describe a novel methodology to exploit the widely used Dynamic Partial Reconfiguration (DPR) support in Field Programmable Gate Arrays (FPGAs) to implant a hardware Trojan in an Advanced Encryption Standard (AES) encryption circuit implemented on a FPGA. The DPR is performed by transferring the required partial configuration bitstream file ...
Keywords: FPGA, fault attack, dynamic partial reconfiguration, AES, hardware Trojan
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13
March 2012 DATE '12: Proceedings of the Conference on Design, Automation and Test in Europe
Publisher: EDA Consortium
Bibliometrics:
Citation Count: 2
Downloads (6 Weeks): 0,   Downloads (12 Months): 0,   Downloads (Overall): 18

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Dynamically reconfigurable architectures, which can offer high performance, are increasingly used in different domains. High-speed reconfiguration process can be carried out by operating at high frequency but can also augment the power consumption. Thus the effort on increasing performance by accelerating the reconfiguration should take into account power consumption constraints. ...
Keywords: ICAP, dynamic partial reconfiguration, power consumption, rapid reconfiguration speed
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14 published by ACM
February 2009 FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Publisher: ACM
Bibliometrics:
Citation Count: 4
Downloads (6 Weeks): 0,   Downloads (12 Months): 0,   Downloads (Overall): 318

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Dynamic Partial Reconfiguration of FPGAs partitions the configurable logic fabric into static and reconfigurable regions. The reconfigurable regions' functionality changes at run time while the static regions continue unperturbed. The reconfigurable and static regions interface via fixed connection points ("bus macros"). We introduce the notion of a fitness score as ...
Keywords: dynamic partial reconfiguration, emips, floor-planning, reconfigurable computing
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15 published by ACM
August 2016 ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Regular Papers and Special Section on Field Programmable Gate Arrays (FPGA) 2015: Volume 9 Issue 4, September 2016
Publisher: ACM
Bibliometrics:
Citation Count: 2
Downloads (6 Weeks): 7,   Downloads (12 Months): 97,   Downloads (Overall): 434

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In this article, we propose an FPGA-based SQL query processing approach exploiting the capabilities of partial dynamic reconfiguration of modern FPGAs. After the analysis of an incoming query, a query-specific hardware processing unit is generated on the fly and loaded on the FPGA for immediate query execution. For each query, ...
Keywords: FPGA, SQL processing, dynamic partial reconfiguration, reconfigurable computing
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16 published by ACM
September 2010 A2CWiC '10: Proceedings of the 1st Amrita ACM-W Celebration on Women in Computing in India
Publisher: ACM
Bibliometrics:
Citation Count: 1
Downloads (6 Weeks): 1,   Downloads (12 Months): 3,   Downloads (Overall): 217

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Reconfigurable architectures possess the flexibility of software solutions as well as the high performance typified by hardware implementations to offer an excellent platform for developing quality-driven embedded applications. Among reconfigurable platforms, the dynamically Reconfigurable Field Programmable Gate Arrays (FPGAs) are most frequently employed for developing adaptive hardware software systems, so ...
Keywords: FPGA, Single Event Upset (SEU), dynamic partial reconfiguration, fault tolerance techniques
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17 published by ACM
September 2012 FPGAworld '12: Proceedings of the Annual FPGA Conference
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 0,   Downloads (12 Months): 1,   Downloads (Overall): 111

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This paper extends the System-on-Chip Wire (SoCWire) Network-On-Chip (NoC) with a reconfigurable router suitable for building FPGA-based NoC. Different configurations of the SoCWireRouter with a varying number of local and multi-dimensional ports have been used to create a number of equivalent networks. The system is prototyped in a FPGA-based PCIexpress ...
Keywords: dynamic partial reconfiguration, network-on-chip, reconfigurable router, SoCWireRouter, SoCWire, FPGA
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18 published by ACM
February 2018 FPGA '18: Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
Publisher: ACM
Bibliometrics:
Citation Count: 0

This paper presents a novel cell architecture for evolvable systolic arrays. HexCell is a tile-able processing element with a hexagonal shape that can be implemented and dynamically reconfigured on field-programmable gate arrays (FPGAs). The cell contains a functional unit, three input ports, and three output ports. It supports two concurrent ...
Keywords: dynamic partial reconfiguration (dpr), evolvable hardware, fpga, hexcell, systolic arrays, virtual reconfiguration circuit (vrc)
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19 published by ACM
November 2007 HPRCTA '07: Proceedings of the 1st international workshop on High-performance reconfigurable computing technology and applications: held in conjunction with SC07
Publisher: ACM
Bibliometrics:
Citation Count: 1
Downloads (6 Weeks): 1,   Downloads (12 Months): 2,   Downloads (Overall): 514

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High-Performance Reconfigurable Computing (HPRC) systems have always been characterized by their high performance and flexibility. Flexibility has been traditionally exploited through the Run-Time Reconfiguration (RTR) provided by most of the available platforms. However, the RTR feature comes with the cost of high configuration overhead which might negatively impact the overall ...
Keywords: dynamic partial reconfiguration, field programmable gate arrays (FPGA), high performance computing, reconfigurable computing
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20 published by ACM
January 2016 ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special Section on RAW2014: Volume 9 Issue 2, February 2016
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 1,   Downloads (12 Months): 34,   Downloads (Overall): 234

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The dynamic partial reconfiguration functionality of FPGAs can be attacked, particularly when the FPGA is remotely located or the configuration bitstreams are sent through insecure networks. The existing FPGA technologies provide some built-in security mechanisms; however, these are often inadequate. The existing solutions still impose a significant impact on the ...
Keywords: Bitstream encryption, and system downgrade prevention, bitstream security, reconfigurable architectures, secure dynamic partial reconfiguration
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Result 1 – 20 of 29
Result page: 1 2



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